diff --git a/flake.lock b/flake.lock index 40f8eec..6d28540 100644 --- a/flake.lock +++ b/flake.lock @@ -94,11 +94,11 @@ "flake-compat_3": { "flake": false, "locked": { - "lastModified": 1668681692, - "narHash": "sha256-Ht91NGdewz8IQLtWZ9LCeNXMSXHUss+9COoqu6JLmXU=", + "lastModified": 1696426674, + "narHash": "sha256-kvjfFW7WAETZlt09AgDn1MrtKzP7t90Vf7vypd3OL1U=", "owner": "edolstra", "repo": "flake-compat", - "rev": "009399224d5e398d03b22badca40a37ac85412a1", + "rev": "0f9255e01c2351cc7d116c072cb317785dd33b33", "type": "github" }, "original": { @@ -112,11 +112,11 @@ "nixpkgs-lib": "nixpkgs-lib" }, "locked": { - "lastModified": 1704982712, - "narHash": "sha256-2Ptt+9h8dczgle2Oo6z5ni5rt/uLMG47UFTR1ry/wgg=", + "lastModified": 1709336216, + "narHash": "sha256-Dt/wOWeW6Sqm11Yh+2+t0dfEWxoMxGBvv3JpIocFl9E=", "owner": "hercules-ci", "repo": "flake-parts", - "rev": "07f6395285469419cf9d078f59b5b49993198c00", + "rev": "f7b3c975cf067e56e7cda6cb098ebe3fb4d74ca2", "type": "github" }, "original": { @@ -127,14 +127,14 @@ }, "flake-utils": { "inputs": { - "systems": "systems" + "systems": "systems_2" }, "locked": { - "lastModified": 1681202837, - "narHash": "sha256-H+Rh19JDwRtpVPAWp64F+rlEtxUWBAQW28eAi3SRSzg=", + "lastModified": 1705309234, + "narHash": "sha256-uNRRNRKmJyCRC/8y1RqBkqWBLM034y4qN7EprSdmgyA=", "owner": "numtide", "repo": "flake-utils", - "rev": "cfacdce06f30d2b68473a46042957675eebb3401", + "rev": "1ef2e671c3b0c19053962c07dbda38332dcebf26", "type": "github" }, "original": { @@ -150,11 +150,11 @@ ] }, "locked": { - "lastModified": 1707204789, - "narHash": "sha256-S3QVfyUPa7zzeyk0TAqr9i9FLwnaO/6zPx4DVCNEeqA=", + "lastModified": 1707205587, + "narHash": "sha256-WzAIbYbflluERLdPC/5epdodjQbR5WiduYS3BjIiGis=", "owner": "chayleaf", "repo": "home-manager", - "rev": "8abb90abf382972e8cd2f3c3b3cdc93c1502b067", + "rev": "acc7c52f80f1aa33239272d786a6e9ba2ffef9f5", "type": "github" }, "original": { @@ -166,11 +166,11 @@ }, "impermanence": { "locked": { - "lastModified": 1703656108, - "narHash": "sha256-hCSUqdFJKHHbER8Cenf5JRzjMlBjIdwdftGQsO0xoJs=", + "lastModified": 1708968331, + "narHash": "sha256-VUXLaPusCBvwM3zhGbRIJVeYluh2uWuqtj4WirQ1L9Y=", "owner": "nix-community", "repo": "impermanence", - "rev": "033643a45a4a920660ef91caa391fbffb14da466", + "rev": "a33ef102a02ce77d3e39c25197664b7a636f9c30", "type": "github" }, "original": { @@ -204,11 +204,11 @@ ] }, "locked": { - "lastModified": 1706482802, - "narHash": "sha256-KXwKTfqFkoPpV8QqaVlpmO8w8rD/jHZL2315RL5QQ8w=", + "lastModified": 1710810847, + "narHash": "sha256-l1DacjuZny7i7YRbxIsa6DhXWoKJZEnM3Em8gt6Fsfk=", "owner": "fufexan", "repo": "nix-gaming", - "rev": "8f354ef64cd18898b8980ecf7fe90118808b514b", + "rev": "03d036f41beaa8c31b2b2261918d248f5c4d45c8", "type": "github" }, "original": { @@ -224,11 +224,11 @@ ] }, "locked": { - "lastModified": 1706411424, - "narHash": "sha256-BzziJYucEZvdCE985vjPoo3ztWcmUiSQ1wJ2CoT6jCc=", + "lastModified": 1710644923, + "narHash": "sha256-0fjbN5GYYDKPyPay0l8gYoH+tFfNqPPwP5sxxBreeA4=", "owner": "nix-community", "repo": "nix-index-database", - "rev": "c782f2a4f6fc94311ab5ef31df2f1149a1856181", + "rev": "e25efda85e39fcdc845e371971ac4384989c4295", "type": "github" }, "original": { @@ -239,11 +239,11 @@ }, "nixos-hardware": { "locked": { - "lastModified": 1706182238, - "narHash": "sha256-Ti7CerGydU7xyrP/ow85lHsOpf+XMx98kQnPoQCSi1g=", + "lastModified": 1710783728, + "narHash": "sha256-eIsfu3c9JUBgm3cURSKTXLEI9Dlk1azo+MWKZVqrmkc=", "owner": "NixOS", "repo": "nixos-hardware", - "rev": "f84eaffc35d1a655e84749228cde19922fcf55f1", + "rev": "1e679b9a9970780cd5d4dfe755a74a8f96d33388", "type": "github" }, "original": { @@ -259,20 +259,14 @@ "nixpkgs": [ "nixpkgs" ], - "nixpkgs-23_05": [ - "nixpkgs" - ], - "nixpkgs-23_11": [ - "nixpkgs" - ], "utils": "utils" }, "locked": { - "lastModified": 1706219574, - "narHash": "sha256-qO+8UErk+bXCq2ybHU4GzXG4Ejk4Tk0rnnTPNyypW4g=", + "lastModified": 1710449465, + "narHash": "sha256-2orO8nfplp6uQJBFqKkj1iyNMC6TysmwbWwbb4osTag=", "owner": "simple-nixos-mailserver", "repo": "nixos-mailserver", - "rev": "e47f3719f1db3e0961a4358d4cb234a0acaa7baf", + "rev": "79c8cfcd5873a85559da6201b116fb38b490d030", "type": "gitlab" }, "original": { @@ -288,11 +282,11 @@ ] }, "locked": { - "lastModified": 1706386221, - "narHash": "sha256-fMBhmJqm6yihdweMmi+NPV4SFj2WXOQSpAwfKoLGyRE=", + "lastModified": 1710972558, + "narHash": "sha256-fA72ql4T4/KgSNxZwZJ1EoEHXjmwt7I/OukHC8NVVF0=", "owner": "chayleaf", "repo": "nixos-router", - "rev": "af7d975e755702b649a386c57b44665d56c80d7a", + "rev": "061cf097417ed363b1e23d11daa7192e4b5f1994", "type": "github" }, "original": { @@ -303,15 +297,16 @@ }, "nixpkgs": { "locked": { - "lastModified": 1706628962, - "narHash": "sha256-BBbgY5OsYMxithcHtoulfAJHTmNxQ41Gr99cHZo4yOM=", + "lastModified": 1710918168, + "narHash": "sha256-T4cnIzAtHDIPlMkiooqv5xOCtE6y6b+KF2A/Iwfy5P4=", "owner": "chayleaf", "repo": "nixpkgs", - "rev": "8a98311cb973d73718e004461d57635b23f632af", + "rev": "2b98d841ceb071e7297844f015dba0ff89fec931", "type": "github" }, "original": { "owner": "chayleaf", + "ref": "ci", "repo": "nixpkgs", "type": "github" } @@ -319,11 +314,11 @@ "nixpkgs-lib": { "locked": { "dir": "lib", - "lastModified": 1703961334, - "narHash": "sha256-M1mV/Cq+pgjk0rt6VxoyyD+O8cOUiai8t9Q6Yyq4noY=", + "lastModified": 1709237383, + "narHash": "sha256-cy6ArO4k5qTx+l5o+0mL9f5fa86tYUX3ozE1S+Txlds=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "b0d36bd0a420ecee3bc916c91886caca87c894e9", + "rev": "1536926ef5621b09bba54035ae2bb6d806d72ac8", "type": "github" }, "original": { @@ -376,11 +371,11 @@ }, "nur": { "locked": { - "lastModified": 1706607970, - "narHash": "sha256-q5W32qx3HhozhAT75AerVqOnhgvNrSyFrjAlu4qNYCU=", + "lastModified": 1710967499, + "narHash": "sha256-f5Ro10NEDq+aZPrSO5f+Hg40iD4BOx2U8NJGomnCqi8=", "owner": "nix-community", "repo": "NUR", - "rev": "d7e286c21530da5d6da54424d64e15de14f7c07a", + "rev": "5ee15db66832970cf391e0c18392779a57a79605", "type": "github" }, "original": { @@ -416,11 +411,11 @@ ] }, "locked": { - "lastModified": 1706580650, - "narHash": "sha256-e6q4Pn1dp3NoQJdMYdyNdDHU5IRBW9i3bHSJ3jThEL0=", + "lastModified": 1710900660, + "narHash": "sha256-PcHmHQvKIOdvAxlqxZ/DPmUMhUUvfp16pRtyW148u/0=", "owner": "oxalica", "repo": "rust-overlay", - "rev": "39e20b3c02caa91c9970beef325a04975d83d77f", + "rev": "549f4db17b5c0c143b1308fcfe9620129c387472", "type": "github" }, "original": { @@ -444,13 +439,31 @@ "type": "github" } }, - "utils": { + "systems_2": { "locked": { - "lastModified": 1605370193, - "narHash": "sha256-YyMTf3URDL/otKdKgtoMChu4vfVL3vCMkRqpGifhUn0=", + "lastModified": 1681028828, + "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=", + "owner": "nix-systems", + "repo": "default", + "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e", + "type": "github" + }, + "original": { + "owner": "nix-systems", + "repo": "default", + "type": "github" + } + }, + "utils": { + "inputs": { + "systems": "systems" + }, + "locked": { + "lastModified": 1709126324, + "narHash": "sha256-q6EQdSeUZOG26WelxqkmR7kArjgWCdw5sfJVHPH/7j8=", "owner": "numtide", "repo": "flake-utils", - "rev": "5021eac20303a61fafe17224c087f5519baed54d", + "rev": "d465f4819400de7c8d874d50b982301f28a84605", "type": "github" }, "original": { diff --git a/flake.nix b/flake.nix index 262f331..874e25d 100644 --- a/flake.nix +++ b/flake.nix @@ -4,7 +4,7 @@ inputs = { #nixpkgs.url = "github:NixOS/nixpkgs/3dc2b4f8166f744c3b3e9ff8224e7c5d74a5424f"; # nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; - nixpkgs.url = "github:chayleaf/nixpkgs"; + nixpkgs.url = "github:chayleaf/nixpkgs/ci"; nixos-hardware.url = "github:NixOS/nixos-hardware"; nix-index-database = { url = "github:nix-community/nix-index-database"; @@ -48,10 +48,6 @@ nixos-mailserver = { url = "gitlab:simple-nixos-mailserver/nixos-mailserver"; inputs.nixpkgs.follows = "nixpkgs"; - # prevent extra input from being in flake.lock - # (this doesn't affect any behavior) - inputs.nixpkgs-23_05.follows = "nixpkgs"; - inputs.nixpkgs-23_11.follows = "nixpkgs"; }; flake-compat = { url = "github:edolstra/flake-compat"; diff --git a/home/modules/gui.nix b/home/modules/gui.nix index 9ee22df..c39d74f 100644 --- a/home/modules/gui.nix +++ b/home/modules/gui.nix @@ -185,17 +185,10 @@ input-default-bindings = false; }; # profiles = { }; - package = pkgs.wrapMpv ((pkgs.mpv-unwrapped.override { - # webp support + package = pkgs.wrapMpv (pkgs.mpv-unwrapped.override { + # many features aren't supported by normal ffmpeg ffmpeg = pkgs.ffmpeg-full; - }).overrideAttrs (old: { - patches = old.patches or [] ++ [ - (pkgs.fetchpatch { - url = "https://github.com/mpv-player/mpv/pull/11648.patch"; - hash = "sha256-rp5VxVD74dY3w5rKct1BwFbruxpHsGk8zwtkkhdJovM="; - }) - ]; - })) { + }) { scripts = with pkgs.mpvScripts; [ thumbnail mpris diff --git a/home/modules/sway.patch b/home/modules/sway.patch index a461592..d863918 100644 --- a/home/modules/sway.patch +++ b/home/modules/sway.patch @@ -1,5 +1,5 @@ diff --git a/include/sway/config.h b/include/sway/config.h -index aa58da53..223efae0 100644 +index f9da1967..fa2d8858 100644 --- a/include/sway/config.h +++ b/include/sway/config.h @@ -50,6 +50,7 @@ enum binding_flags { @@ -24,10 +24,10 @@ index 979e178f..d17458ea 100644 break; } diff --git a/sway/input/keyboard.c b/sway/input/keyboard.c -index c3bf4fbb..78ef8e61 100644 +index 8927287f..3faff953 100644 --- a/sway/input/keyboard.c +++ b/sway/input/keyboard.c -@@ -162,8 +162,9 @@ static void get_active_binding(const struct sway_shortcut_state *state, +@@ -161,8 +161,9 @@ static void get_active_binding(const struct sway_shortcut_state *state, bool binding_locked = (binding->flags & BINDING_LOCKED) != 0; bool binding_inhibited = (binding->flags & BINDING_INHIBITED) != 0; bool binding_release = binding->flags & BINDING_RELEASE; @@ -38,7 +38,7 @@ index c3bf4fbb..78ef8e61 100644 release != binding_release || locked > binding_locked || inhibited > binding_inhibited || -@@ -175,7 +176,42 @@ static void get_active_binding(const struct sway_shortcut_state *state, +@@ -174,7 +175,42 @@ static void get_active_binding(const struct sway_shortcut_state *state, } bool match = false; @@ -83,21 +83,18 @@ index c3bf4fbb..78ef8e61 100644 for (size_t j = 0; j < state->npressed; j++) { uint32_t key = *(uint32_t *)binding->keys->items[j]; diff --git a/sway/sway.5.scd b/sway/sway.5.scd -index 25082c41..268e0526 100644 +index 7e58b528..794965b9 100644 --- a/sway/sway.5.scd +++ b/sway/sway.5.scd -@@ -389,8 +389,8 @@ runtime. - for_window move container to output +@@ -390,6 +390,7 @@ runtime. *bindsym* [--whole-window] [--border] [--exclude-titlebar] [--release] [--locked] \ --[--to-code] [--input-device=] [--no-warn] [--no-repeat] [Group<1-4>+] \ -- -+[--to-code] [--input-device=] [--no-warn] [--no-repeat] [--allow-other] \ -+[Group<1-4>+] + [--to-code] [--input-device=] [--no-warn] [--no-repeat] [--inhibited] \ ++[--allow-other] \ + [Group<1-4>+] Binds _key combo_ to execute the sway command _command_ when pressed. You may use XKB key names here (*wev*(1) is a good tool for discovering these). - With the flag _--release_, the command is executed when the key combo is -@@ -419,6 +419,11 @@ runtime. +@@ -419,6 +420,11 @@ runtime. repeatedly when the key is held, according to the repeat settings specified in the input configuration. diff --git a/pkgs/_sources/generated.json b/pkgs/_sources/generated.json index d4e4180..af165a4 100644 --- a/pkgs/_sources/generated.json +++ b/pkgs/_sources/generated.json @@ -22,24 +22,24 @@ "pinned": false, "src": { "name": null, - "sha256": "sha256-5fEYhazqXcMENjp+37IcF5U81vZ9bPDkS0siUVi9mdg=", + "sha256": "sha256-wCIffeayOy3kEwmIKB7e+NrliuSpKXoVYC334fxVB3U=", "type": "url", - "url": "https://github.com/GloriousEggroll/proton-ge-custom/releases/download/GE-Proton8-27/GE-Proton8-27.tar.gz" + "url": "https://github.com/GloriousEggroll/proton-ge-custom/releases/download/GE-Proton9-1/GE-Proton9-1.tar.gz" }, - "version": "GE-Proton8-27" + "version": "GE-Proton9-1" }, "searxng": { "cargoLocks": null, - "date": "2024-01-25", + "date": "2024-03-15", "extract": null, "name": "searxng", "passthru": null, "pinned": false, "src": { - "sha256": "sha256-QW1xC6RsHpn5P/QHjyc3O24tSmLvRCVIJwNqPyp1DV0=", + "sha256": "sha256-BqVnp/lByAMr/LOCGkuXCYsomu9hRBGXK3DbBQX10TA=", "type": "tarball", - "url": "https://github.com/searxng/searxng/archive/8c73aa772b7d4446f77be82d8f9d9eef1e348deb.tar.gz" + "url": "https://github.com/searxng/searxng/archive/e2af3e49702f6fb40e1614f826544dc3b03bca2f.tar.gz" }, - "version": "8c73aa772b7d4446f77be82d8f9d9eef1e348deb" + "version": "e2af3e49702f6fb40e1614f826544dc3b03bca2f" } } \ No newline at end of file diff --git a/pkgs/_sources/generated.nix b/pkgs/_sources/generated.nix index 4ae7758..2a3fb49 100644 --- a/pkgs/_sources/generated.nix +++ b/pkgs/_sources/generated.nix @@ -12,19 +12,19 @@ }; proton-ge = { pname = "proton-ge"; - version = "GE-Proton8-27"; + version = "GE-Proton9-1"; src = fetchurl { - url = "https://github.com/GloriousEggroll/proton-ge-custom/releases/download/GE-Proton8-27/GE-Proton8-27.tar.gz"; - sha256 = "sha256-5fEYhazqXcMENjp+37IcF5U81vZ9bPDkS0siUVi9mdg="; + url = "https://github.com/GloriousEggroll/proton-ge-custom/releases/download/GE-Proton9-1/GE-Proton9-1.tar.gz"; + sha256 = "sha256-wCIffeayOy3kEwmIKB7e+NrliuSpKXoVYC334fxVB3U="; }; }; searxng = { pname = "searxng"; - version = "8c73aa772b7d4446f77be82d8f9d9eef1e348deb"; + version = "e2af3e49702f6fb40e1614f826544dc3b03bca2f"; src = fetchTarball { - url = "https://github.com/searxng/searxng/archive/8c73aa772b7d4446f77be82d8f9d9eef1e348deb.tar.gz"; - sha256 = "sha256-QW1xC6RsHpn5P/QHjyc3O24tSmLvRCVIJwNqPyp1DV0="; + url = "https://github.com/searxng/searxng/archive/e2af3e49702f6fb40e1614f826544dc3b03bca2f.tar.gz"; + sha256 = "sha256-BqVnp/lByAMr/LOCGkuXCYsomu9hRBGXK3DbBQX10TA="; }; - date = "2024-01-25"; + date = "2024-03-15"; }; } diff --git a/pkgs/firefox-addons/generated.nix b/pkgs/firefox-addons/generated.nix index 22a83b4..77f9868 100644 --- a/pkgs/firefox-addons/generated.nix +++ b/pkgs/firefox-addons/generated.nix @@ -17,16 +17,16 @@ "tabs" "declarativeNetRequestWithHostAccess" "" - ]; + ]; platforms = platforms.all; - }; }; + }; "rikaitan" = buildFirefoxXpiAddon { pname = "rikaitan"; - version = "24.1.22.0"; + version = "24.3.7.1"; addonId = "tatsu@autistici.org"; - url = "https://addons.mozilla.org/firefox/downloads/file/4224979/rikaitan-24.1.22.0.xpi"; - sha256 = "7df217a68077d45b9f41fe0170193c9224abc2a543c121429ebef4e7e857b0df"; + url = "https://addons.mozilla.org/firefox/downloads/file/4246908/rikaitan-24.3.7.1.xpi"; + sha256 = "db849343b029b2f1b510cc66032157502e3fe9e6168072d27e8aad9867b6ec17"; meta = with lib; { homepage = "https://github.com/Ajatt-Tools/rikaitan"; @@ -41,10 +41,10 @@ "http://*/*" "https://*/*" "file://*/*" - ]; + ]; platforms = platforms.all; - }; }; + }; "youtube-nonstop" = buildFirefoxXpiAddon { pname = "youtube-nonstop"; version = "0.9.2"; @@ -59,8 +59,8 @@ mozPermissions = [ "https://www.youtube.com/*" "https://music.youtube.com/*" - ]; + ]; platforms = platforms.all; - }; }; - } + }; + } \ No newline at end of file diff --git a/pkgs/home-daemon/Cargo.lock b/pkgs/home-daemon/Cargo.lock index c843b62..3c55598 100644 --- a/pkgs/home-daemon/Cargo.lock +++ b/pkgs/home-daemon/Cargo.lock @@ -11,6 +11,27 @@ dependencies = [ "memchr", ] +[[package]] +name = "alsa" +version = "0.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "37fe60779335388a88c01ac6c3be40304d1e349de3ada3b15f7808bb90fa9dce" +dependencies = [ + "alsa-sys", + "bitflags 2.5.0", + "libc", +] + +[[package]] +name = "alsa-sys" +version = "0.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "db8fee663d06c4e303404ef5f40488a53e062f89ba8bfed81f42325aafad1527" +dependencies = [ + "libc", + "pkg-config", +] + [[package]] name = "async-broadcast" version = "0.5.0" @@ -53,7 +74,7 @@ dependencies = [ "slab", "socket2", "waker-fn", - "windows-sys", + "windows-sys 0.42.0", ] [[package]] @@ -84,7 +105,7 @@ checksum = "3b015a331cc64ebd1774ba119538573603427eaace0a1950c423ab971f903796" dependencies = [ "proc-macro2", "quote", - "syn", + "syn 1.0.107", ] [[package]] @@ -101,7 +122,7 @@ checksum = "eff18d764974428cf3a9328e23fc5c986f5fbed46e6cd4cdf42544df5d297ec1" dependencies = [ "proc-macro2", "quote", - "syn", + "syn 1.0.107", ] [[package]] @@ -110,12 +131,38 @@ version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa" +[[package]] +name = "bindgen" +version = "0.69.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a00dc851838a2120612785d195287475a3ac45514741da670b735818822129a0" +dependencies = [ + "bitflags 2.5.0", + "cexpr", + "clang-sys", + "itertools", + "lazy_static", + "lazycell", + "proc-macro2", + "quote", + "regex", + "rustc-hash", + "shlex", + "syn 2.0.53", +] + [[package]] name = "bitflags" version = "1.3.2" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a" +[[package]] +name = "bitflags" +version = "2.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cf4b9d6a944f767f8e5e0db018570623c85f3d925ac718db4e06d0187adb21c1" + [[package]] name = "block-buffer" version = "0.10.3" @@ -125,6 +172,12 @@ dependencies = [ "generic-array", ] +[[package]] +name = "bumpalo" +version = "3.15.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7ff69b9dd49fd426c69a0db9fc04dd934cdb6645ff000864d98f7e2af8830eaa" + [[package]] name = "byteorder" version = "1.4.3" @@ -142,6 +195,24 @@ name = "cc" version = "1.0.78" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "a20104e2335ce8a659d6dd92a51a767a0c062599c73b343fd152cb401e828c3d" +dependencies = [ + "jobserver", +] + +[[package]] +name = "cesu8" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6d43a04d8753f35258c91f8ec639f792891f748a1edbd759cf1dcea3382ad83c" + +[[package]] +name = "cexpr" +version = "0.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6fac387a98bb7c37292057cffc56d62ecb629900026402633ae9160df93a8766" +dependencies = [ + "nom", +] [[package]] name = "cfg-if" @@ -149,6 +220,27 @@ version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd" +[[package]] +name = "clang-sys" +version = "1.7.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "67523a3b4be3ce1989d607a828d036249522dd9c1c8de7f4dd2dae43a37369d1" +dependencies = [ + "glob", + "libc", + "libloading", +] + +[[package]] +name = "combine" +version = "4.6.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = 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= "0.15.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "873dab07c8f743075e57f524c583985fbaf745602acbe916a01539364369a779" +dependencies = [ + "alsa", + "core-foundation-sys", + "coreaudio-rs", + "dasp_sample", + "jni", + "js-sys", + "libc", + "mach2", + "ndk", + "ndk-context", + "oboe", + "wasm-bindgen", + "wasm-bindgen-futures", + "web-sys", + "windows", +] + [[package]] name = "cpufeatures" version = "0.2.5" @@ -186,6 +327,12 @@ dependencies = [ "typenum", ] +[[package]] +name = "dasp_sample" +version = "0.11.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0c87e182de0887fd5361989c677c4e8f5000cd9491d6d563161a8f3a5519fc7f" + [[package]] name = "derivative" version = "2.2.0" @@ -194,7 +341,7 @@ checksum = "fcc3dd5e9e9c0b295d6e1e4d811fb6f157d5ffd784b8d202fc62eac8035a770b" dependencies = [ "proc-macro2", "quote", - "syn", + "syn 1.0.107", ] [[package]] @@ -228,14 +375,10 @@ dependencies = [ ] [[package]] -name = "home-daemon" -version = "0.1.0" -dependencies = [ - "futures-util", - "swayipc-async", - "tokio", - "zbus", -] +name = "either" +version = "1.10.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "11157ac094ffbdde99aa67b23417ebdd801842852b500e395a45a9c0aac03e4a" [[package]] name = "enumflags2" @@ -255,7 +398,7 @@ checksum = "f58dc3c5e468259f19f2d46304a6b28f1c3d034442e14b322d2b850e36f6d5ae" dependencies = [ "proc-macro2", "quote", - "syn", + "syn 1.0.107", ] [[package]] @@ -308,7 +451,7 @@ checksum = "bdfb8ce053d86b91919aad980c220b1fb8401a9394410e1c289ed7e66b61835d" dependencies = [ "proc-macro2", "quote", - "syn", + "syn 1.0.107", ] [[package]] @@ -359,6 +502,12 @@ dependencies = [ "wasi", ] +[[package]] +name = "glob" +version = "0.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d2fabcfbdc87f4758337ca535fb41a6d701b65693ce38287d856d1674551ec9b" + [[package]] name = "hashbrown" version = "0.12.3" @@ -371,6 +520,17 @@ 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"1a87aa2bb7d2af34197c04845522473242e1aa17c12f4935d5856491a7fb8c97" +dependencies = [ + "cesu8", + "cfg-if", + "combine", + "jni-sys", + "log", + "thiserror", + "walkdir", + "windows-sys 0.45.0", +] + +[[package]] +name = "jni-sys" +version = "0.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8eaf4bc02d17cbdd7ff4c7438cafcdf7fb9a4613313ad11b4f8fefe7d3fa0130" + +[[package]] +name = "jobserver" +version = "0.1.28" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ab46a6e9526ddef3ae7f787c06f0f2600639ba80ea3eade3d8e670a2230f51d6" +dependencies = [ + "libc", +] + +[[package]] +name = "js-sys" +version = "0.3.69" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "29c15563dc2726973df627357ce0c9ddddbea194836909d655df6a75d2cf296d" +dependencies = [ + "wasm-bindgen", +] + [[package]] name = "lazy_static" version = "1.4.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "e2abad23fbc42b3700f2f279844dc832adb2b2eb069b2df918f455c4e18cc646" +[[package]] +name = "lazycell" +version = "1.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "830d08ce1d1d941e6b30645f1a0eb5643013d835ce3779a5fc208261dbe10f55" + [[package]] name = "libc" version = "0.2.139" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "201de327520df007757c1f0adce6e827fe8562fbc28bfd9c15571c66ca1f5f79" +[[package]] +name = "libloading" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0c2a198fb6b0eada2a8df47933734e6d35d350665a33a3593d7164fa52c75c19" +dependencies = [ + "cfg-if", + "windows-targets 0.52.4", +] + [[package]] name = "lock_api" version = "0.4.9" @@ -427,6 +652,15 @@ dependencies = [ "cfg-if", ] +[[package]] +name = "mach2" +version = "0.4.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "19b955cdeb2a02b9117f121ce63aa52d08ade45de53e48fe6a38b39c10f6f709" +dependencies = [ + "libc", +] + [[package]] name = "memchr" version = "2.5.0" @@ -442,6 +676,12 @@ dependencies = [ "autocfg", ] +[[package]] +name = "minimal-lexical" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "68354c5c6bd36d73ff3feceb05efa59b6acb7626617f4962be322a825e61f79a" + [[package]] name = "mio" version = "0.8.5" @@ -451,7 +691,36 @@ dependencies = [ "libc", "log", "wasi", - "windows-sys", + "windows-sys 0.42.0", +] + +[[package]] +name = "ndk" +version = "0.8.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2076a31b7010b17a38c01907c45b945e8f11495ee4dd588309718901b1f7a5b7" +dependencies = [ + "bitflags 2.5.0", + "jni-sys", + "log", + "ndk-sys", + "num_enum", + "thiserror", +] + +[[package]] +name = "ndk-context" +version = "0.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = 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"registry+https://github.com/rust-lang/crates.io-index" +checksum = "ed3955f1a9c7c0c15e092f9c887db08b1fc683305fdf6eb6684f22555355e202" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.53", +] + +[[package]] +name = "num-traits" +version = "0.2.18" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "da0df0e5185db44f69b44f26786fe401b6c293d1907744beaa7fa62b2e5a517a" +dependencies = [ + "autocfg", +] + +[[package]] +name = "num_enum" +version = "0.7.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "02339744ee7253741199f897151b38e72257d13802d4ee837285cc2990a90845" +dependencies = [ + "num_enum_derive", +] + +[[package]] +name = "num_enum_derive" +version = "0.7.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "681030a937600a36906c185595136d26abfebb4aa9c65701cefcaf8578bb982b" +dependencies = [ + "proc-macro-crate", + "proc-macro2", + "quote", + "syn 2.0.53", +] + +[[package]] +name = "oboe" +version = "0.6.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e8b61bebd49e5d43f5f8cc7ee2891c16e0f41ec7954d36bcb6c14c5e0de867fb" +dependencies = [ + "jni", + "ndk", + "ndk-context", + "num-derive", + "num-traits", + "oboe-sys", +] + +[[package]] +name = "oboe-sys" +version = "0.6.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6c8bb09a4a2b1d668170cfe0a7d5bc103f8999fb316c98099b6a9939c9f2e79d" +dependencies = [ + "cc", +] + [[package]] name = "once_cell" version = "1.17.0" @@ -519,7 +862,7 @@ dependencies = [ "libc", "redox_syscall", "smallvec", - "windows-sys", + "windows-sys 0.42.0", ] [[package]] @@ -534,6 +877,12 @@ version = "0.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "8b870d8c151b6f2fb93e84a13146138f05d02ed11c7e7c54f8826aaaf7c9f184" +[[package]] +name = "pkg-config" +version = "0.3.30" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = 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"9aec5da331524158c6d1a4ac0ab1541149c0b9505fde06423b02f5ef0106b9f0" + +[[package]] +name = "windows_x86_64_msvc" +version = "0.52.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "32b752e52a2da0ddfbdbcc6fceadfeede4c939ed16d13e648833a61dfb611ed8" [[package]] name = "zbus" @@ -1080,7 +1666,7 @@ dependencies = [ "proc-macro2", "quote", "regex", - "syn", + "syn 1.0.107", ] [[package]] @@ -1117,5 +1703,5 @@ dependencies = [ "proc-macro-crate", "proc-macro2", "quote", - "syn", + "syn 1.0.107", ] diff --git a/pkgs/home-daemon/Cargo.toml b/pkgs/home-daemon/Cargo.toml index bd3d1d8..e0481b0 100644 --- a/pkgs/home-daemon/Cargo.toml +++ b/pkgs/home-daemon/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "home-daemon" -version = "0.1.0" +version = "0.2.0" edition = "2021" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html @@ -9,6 +9,7 @@ edition = "2021" zbus = { version = "3", features = ["tokio"] } futures-util = "0.3" swayipc-async = "2" +cpal = "0.15" [dependencies.tokio] version = "1" diff --git a/pkgs/home-daemon/default.nix b/pkgs/home-daemon/default.nix index 50ea3d0..dba80ad 100644 --- a/pkgs/home-daemon/default.nix +++ b/pkgs/home-daemon/default.nix @@ -1,9 +1,18 @@ -{ lib, rustPlatform, nix-gitignore }: +{ lib +, rustPlatform +, nix-gitignore +, pkg-config +, alsa-lib +}: + rustPlatform.buildRustPackage { pname = "home-daemon"; - version = "0.1"; + version = "0.2.0"; - src = nix-gitignore.gitignoreSource ["/target" "default.nix"] (lib.cleanSource ./.); + nativeBuildInputs = [ pkg-config ]; + buildInputs = [ alsa-lib ]; + + src = nix-gitignore.gitignoreSource [ "/target" "default.nix" ] ./.; cargoLock.lockFile = ./Cargo.lock; diff --git a/pkgs/home-daemon/shell.nix b/pkgs/home-daemon/shell.nix index 7bd1d27..5df9dca 100644 --- a/pkgs/home-daemon/shell.nix +++ b/pkgs/home-daemon/shell.nix @@ -1,8 +1,8 @@ -{ pkgs ? import {} }: +{ pkgs ? import {}, lib ? pkgs.lib }: -pkgs.mkShell { +pkgs.mkShell rec { name = "shell-rust"; - buildInputs = [ - pkgs.rustc pkgs.cargo - ]; + nativeBuildInputs = with pkgs; [ pkg-config rustc cargo ]; + buildInputs = with pkgs; [ alsa-lib ]; + LD_LIBRARY_PATH = "${lib.makeLibraryPath buildInputs}"; } diff --git a/pkgs/home-daemon/src/main.rs b/pkgs/home-daemon/src/main.rs index 9fbf5e4..9581e64 100644 --- a/pkgs/home-daemon/src/main.rs +++ b/pkgs/home-daemon/src/main.rs @@ -1,3 +1,4 @@ +use cpal::{traits::{DeviceTrait, HostTrait, StreamTrait}, SampleFormat}; use futures_util::stream::StreamExt; use std::collections::HashSet; use swayipc_async::{Connection, Event, EventType, WindowChange}; @@ -8,14 +9,26 @@ async fn main() { let _ses_dbus = Box::leak(Box::new(zbus::Connection::session().await.unwrap())); let mut handlers = Vec::>::new(); + let mut panic = true; for args in std::env::args().skip(1) { handlers.push(match args.as_str() { "system76-scheduler" => Box::new(System76::new(sys_dbus).await), + "empty-sound" => { + panic = false; + tokio::spawn(async { + play_empty_sound().await; + }); + continue; + } _ => panic!("handler not supported"), }) } if handlers.is_empty() { - panic!("no handlers set up"); + if panic { + panic!("no handlers set up"); + } else { + futures_util::future::pending::<()>().await; + } } let mut subs = HashSet::new(); @@ -29,11 +42,11 @@ async fn main() { } } -async fn start(subs: &[EventType], handlers: &mut [Box]) -> Result<(), swayipc_async::Error> { - let mut events = Connection::new() - .await? - .subscribe(&subs) - .await?; +async fn start( + subs: &[EventType], + handlers: &mut [Box], +) -> Result<(), swayipc_async::Error> { + let mut events = Connection::new().await?.subscribe(&subs).await?; while let Some(event) = events.next().await { match event { Ok(event) => { @@ -42,17 +55,50 @@ async fn start(subs: &[EventType], handlers: &mut [Box]) -> } } Err(err) => match err { - swayipc_async::Error::Io(_) + swayipc_async::Error::Io(_) | swayipc_async::Error::InvalidMagic(_) - | swayipc_async::Error::SubscriptionFailed(_) - => return Err(err), + | swayipc_async::Error::SubscriptionFailed(_) => return Err(err), _ => {} - } + }, } } Ok(()) } +async fn play_empty_sound() { + let device = cpal::default_host() + .default_output_device() + .expect("no output device available"); + let supported_config = device + .supported_output_configs() + .unwrap() + .find(|config| { + config.sample_format() == SampleFormat::F32 + && (config.min_sample_rate()..=config.max_sample_rate()) + .contains(&cpal::SampleRate(44100)) + && config.channels() == 1 + }) + .unwrap() + .with_sample_rate(cpal::SampleRate(44100)); + let config = supported_config.into(); + let stream = Box::leak(Box::new( + device + .build_output_stream( + &config, + |data: &mut [f32], _: &cpal::OutputCallbackInfo| { + for sample in data.iter_mut() { + *sample = 1.0 / 1985.0; + } + }, + |err| eprintln!("an error occurred on the output audio stream: {}", err), + None, + ) + .unwrap(), + )); + stream.play().unwrap(); + futures_util::future::pending::<()>().await; +} + trait SwayIpcHandler { fn register(&mut self, subs: &mut HashSet); fn handle(&mut self, event: &Event); @@ -97,4 +143,3 @@ impl SwayIpcHandler for System76<'static> { } } } - diff --git a/system/hardware/oneplus-enchilada/config_fixes.patch b/system/hardware/oneplus-enchilada/config_fixes.patch index 2bbfd45..55517e0 100644 --- a/system/hardware/oneplus-enchilada/config_fixes.patch +++ b/system/hardware/oneplus-enchilada/config_fixes.patch @@ -1,10 +1,10 @@ diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index b60aa1f8934..0e3191950d5 100644 +index e6cf3e5d63c..54d5d7c10e4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig -@@ -1317,8 +1317,9 @@ CONFIG_QCOM_AOSS_QMP=y +@@ -1351,8 +1351,9 @@ CONFIG_MTK_SVS=m + CONFIG_QCOM_AOSS_QMP=y CONFIG_QCOM_COMMAND_DB=y - CONFIG_QCOM_CPR=y CONFIG_QCOM_GENI_SE=y -CONFIG_QCOM_LLCC=m -CONFIG_QCOM_OCMEM=m diff --git a/system/hardware/oneplus-enchilada/linux_6_7.patch b/system/hardware/oneplus-enchilada/linux_6_8.patch similarity index 91% rename from system/hardware/oneplus-enchilada/linux_6_7.patch rename to system/hardware/oneplus-enchilada/linux_6_8.patch index 4531a28..bd93ff0 100644 --- a/system/hardware/oneplus-enchilada/linux_6_7.patch +++ b/system/hardware/oneplus-enchilada/linux_6_8.patch @@ -183,7 +183,7 @@ index f2808cb4d99..745e57c0517 100644 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/leds/qcom,spmi-flash-led.yaml b/Documentation/devicetree/bindings/leds/qcom,spmi-flash-led.yaml -index a8736fd5a53..c389d1955bd 100644 +index 1ba607685f5..7868569ab6d 100644 --- a/Documentation/devicetree/bindings/leds/qcom,spmi-flash-led.yaml +++ b/Documentation/devicetree/bindings/leds/qcom,spmi-flash-led.yaml @@ -23,11 +23,11 @@ properties: @@ -199,119 +199,6 @@ index a8736fd5a53..c389d1955bd 100644 - const: qcom,spmi-flash-led reg: -diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx519.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx519.yaml -new file mode 100644 -index 00000000000..4ba318581aa ---- /dev/null -+++ b/Documentation/devicetree/bindings/media/i2c/sony,imx519.yaml -@@ -0,0 +1,107 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/media/i2c/sony,imx519.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sony 1/2.5-Inch 16Mpixel CMOS Digital Image Sensor -+ -+maintainers: -+ - Lee Jackson -+ -+description: -+ The Sony IMX519 is a 1/2.5-inch CMOS active pixel digital image sensor -+ with an active array size of 4656H x 3496V. It is programmable through -+ I2C interface. The I2C address is fixed to 0x1A as per sensor data sheet. -+ Image data is sent through MIPI CSI-2, which is configured as either 2 or -+ 4 data lanes. -+ -+properties: -+ compatible: -+ const: sony,imx519 -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ maxItems: 1 -+ -+ vdig-supply: -+ description: -+ Digital I/O voltage supply, 1.05 volts -+ -+ vana-supply: -+ description: -+ Analog voltage supply, 2.8 volts -+ -+ vddl-supply: -+ description: -+ Digital core voltage supply, 1.8 volts -+ -+ reset-gpios: -+ description: -+ Reference to the GPIO connected to the xclr pin, if any. -+ Must be released (set high) after all supplies and INCK are applied. -+ -+ port: -+ $ref: /schemas/graph.yaml#/$defs/port-base -+ additionalProperties: false -+ -+ properties: -+ endpoint: -+ $ref: /schemas/media/video-interfaces.yaml# -+ unevaluatedProperties: false -+ -+ properties: -+ data-lanes: -+ anyOf: -+ - items: -+ - const: 1 -+ - const: 2 -+ - items: -+ - const: 1 -+ - const: 2 -+ - const: 3 -+ - const: 4 -+ -+ required: -+ - data-lanes -+ - link-frequencies -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - vana-supply -+ - vdig-supply -+ - vddl-supply -+ - port -+ -+additionalProperties: false -+ -+examples: -+ - | -+ i2c { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ sensor@1a { -+ compatible = "sony,imx519"; -+ reg = <0x1a>; -+ clocks = <&imx519_clk>; -+ vana-supply = <&imx519_vana>; /* 2.8v */ -+ vdig-supply = <&imx519_vdig>; /* 1.05v */ -+ vddl-supply = <&imx519_vddl>; /* 1.8v */ -+ -+ port { -+ imx519_ep: endpoint { -+ remote-endpoint = <&csi1_ep>; -+ data-lanes = <1 2>; -+ clock-noncontinuous; -+ link-frequencies = /bits/ 64 <408000000>; -+ }; -+ }; -+ }; -+ }; -+ -+... diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml index 7758a55dd32..874ca4157fb 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml @@ -639,10 +526,10 @@ index b4557462edd..d43336e64d6 100644 - Used to describe multitouch input events. Please see diff --git a/MAINTAINERS b/MAINTAINERS -index a7c4cf8201e..5426ae32c1f 100644 +index 1aabf1c15bb..b8b4d2e0a2c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -6811,6 +6811,11 @@ S: Maintained +@@ -6879,6 +6879,11 @@ S: Maintained F: Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml F: drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c @@ -654,34 +541,6 @@ index a7c4cf8201e..5426ae32c1f 100644 DRM DRIVER FOR SITRONIX ST7586 PANELS M: David Lechner S: Maintained -@@ -20170,6 +20175,15 @@ T: git git://linuxtv.org/media_tree.git - F: Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml - F: drivers/media/i2c/imx415.c - -+SONY IMX519 SENSOR DRIVER -+M: Arducam Kernel Maintenance -+M: Lee Jackson -+L: linux-media@vger.kernel.org -+S: Maintained -+T: git git://linuxtv.org/media_tree.git -+F: Documentation/devicetree/bindings/media/i2c/sony,imx519.yaml -+F: drivers/media/i2c/imx519.c -+ - SONY MEMORYSTICK SUBSYSTEM - M: Maxim Levitsky - M: Alex Dubov -diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile -index d6cb840b705..28f3a66dc2f 100644 ---- a/arch/arm64/boot/dts/qcom/Makefile -+++ b/arch/arm64/boot/dts/qcom/Makefile -@@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb - dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb - dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb - dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb -+dtb-$(CONFIG_ARCH_QCOM) += sc7180-tcl-b220g.dtb - dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb - dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb - dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index cd3f0790fd4..2ceee5ff81b 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -732,33 +591,10 @@ index cd3f0790fd4..2ceee5ff81b 100644 }; }; diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi -index d46e591e72b..2b952a5b752 100644 +index 0911fb08ed6..8aeaf2ae1fd 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi -@@ -5,12 +5,14 @@ - * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. - */ - -+#include - #include - #include - #include - #include - #include - #include -+#include - #include - - / { -@@ -150,6 +152,7 @@ scm: scm { - clocks = <&rpmcc RPM_SMD_CE1_CLK>; - clock-names = "core"; - #reset-cells = <1>; -+ interconnects = <&system_noc MASTER_CRYPTO_CORE0 0 &bimc SLAVE_EBI1 0>; - }; - }; - -@@ -170,32 +173,35 @@ psci { +@@ -175,33 +175,35 @@ psci { CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; @@ -791,1662 +627,15 @@ index d46e591e72b..2b952a5b752 100644 +#if 0 CLUSTER_PD: power-domain-cpu-cluster { #power-domain-cells = <0>; -+ power-domains = <&mpm>; + power-domains = <&mpm>; domain-idle-states = <&CLUSTER_SLEEP>; }; +#endif }; rpm: remoteproc { -@@ -261,6 +267,24 @@ rpmpd_opp_turbo_plus: opp8 { - }; - }; - }; -+ -+ mpm: interrupt-controller { -+ compatible = "qcom,mpm"; -+ qcom,rpm-msg-ram = <&apss_mpm>; -+ interrupts = ; -+ mboxes = <&apcs_glb 1>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ #power-domain-cells = <0>; -+ interrupt-parent = <&intc>; -+ qcom,mpm-pin-count = <96>; -+ qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ -+ <5 296>, /* Soundwire master_irq */ -+ <12 422>, /* DWC3 ss_phy_irq */ -+ <24 79>, /* Soundwire wake_irq */ -+ <86 183>, /* MPM wake, SPMI */ -+ <90 260>; /* DWC3 dp/dm_hs_phy_irq */ -+ }; - }; - - reserved_memory: reserved-memory { -@@ -424,6 +448,7 @@ tlmm: pinctrl@500000 { - interrupts = ; - gpio-controller; - gpio-ranges = <&tlmm 0 0 127>; -+ wakeup-parent = <&mpm>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -@@ -668,6 +693,33 @@ usb_qmpphy: phy@1615000 { - status = "disabled"; - }; - -+ system_noc: interconnect@1880000 { -+ compatible = "qcom,qcm2290-snoc"; -+ reg = <0x0 0x01880000 0x0 0x60200>; -+ #interconnect-cells = <2>; -+ -+ qup_virt: interconnect-qup { -+ compatible = "qcom,qcm2290-qup-virt"; -+ #interconnect-cells = <2>; -+ }; -+ -+ mmnrt_virt: interconnect-mmnrt { -+ compatible = "qcom,qcm2290-mmnrt-virt"; -+ #interconnect-cells = <2>; -+ }; -+ -+ mmrt_virt: interconnect-mmrt { -+ compatible = "qcom,qcm2290-mmrt-virt"; -+ #interconnect-cells = <2>; -+ }; -+ }; -+ -+ config_noc: interconnect@1900000 { -+ compatible = "qcom,qcm2290-cnoc"; -+ reg = <0x0 0x01900000 0x0 0x8200>; -+ #interconnect-cells = <2>; -+ }; -+ - qfprom@1b44000 { - compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; - reg = <0x0 0x01b44000 0x0 0x3000>; -@@ -680,6 +732,60 @@ qusb2_hstx_trim: hstx-trim@25b { - }; - }; - -+ pmu@1b8e300 { -+ compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon"; -+ reg = <0 0x01b8e300 0 0x600>; -+ interrupts = ; -+ -+ operating-points-v2 = <&cpu_bwmon_opp_table>; -+ interconnects = <&bimc MASTER_APPSS_PROC 1 -+ &bimc SLAVE_EBI1 1>; -+ -+ cpu_bwmon_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-0 { -+ opp-peak-kBps = <1525000>; -+ }; -+ -+ opp-1 { -+ opp-peak-kBps = <2288000>; -+ }; -+ -+ opp-2 { -+ opp-peak-kBps = <3440000>; -+ }; -+ -+ opp-3 { -+ opp-peak-kBps = <4173000>; -+ }; -+ -+ opp-4 { -+ opp-peak-kBps = <5195000>; -+ }; -+ -+ opp-5 { -+ opp-peak-kBps = <5859000>; -+ }; -+ -+ opp-6 { -+ opp-peak-kBps = <7759000>; -+ }; -+ -+ opp-7 { -+ opp-peak-kBps = <10322000>; -+ }; -+ -+ opp-8 { -+ opp-peak-kBps = <11863000>; -+ }; -+ -+ opp-9 { -+ opp-peak-kBps = <13763000>; -+ }; -+ }; -+ }; -+ - spmi_bus: spmi@1c40000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x01c40000 0x0 0x1100>, -@@ -692,7 +798,7 @@ spmi_bus: spmi@1c40000 { - "obsrvr", - "intr", - "cnfg"; -- interrupts = ; -+ interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "periph_irq"; - qcom,ee = <0>; - qcom,channel = <0>; -@@ -707,8 +813,8 @@ tsens0: thermal-sensor@4411000 { - reg = <0x0 0x04411000 0x0 0x1ff>, - <0x0 0x04410000 0x0 0x8>; - #qcom,sensors = <10>; -- interrupts = , -- ; -+ interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, -+ <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; -@@ -720,9 +826,22 @@ rng: rng@4453000 { - clock-names = "core"; - }; - -+ bimc: interconnect@4480000 { -+ compatible = "qcom,qcm2290-bimc"; -+ reg = <0x0 0x04480000 0x0 0x80000>; -+ #interconnect-cells = <2>; -+ }; -+ - rpm_msg_ram: sram@45f0000 { -- compatible = "qcom,rpm-msg-ram"; -+ compatible = "qcom,rpm-msg-ram", "mmio-sram"; - reg = <0x0 0x045f0000 0x0 0x7000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x0 0x045f0000 0x7000>; -+ -+ apss_mpm: sram@1b8 { -+ reg = <0x1b8 0x48>; -+ }; - }; - - sram@4690000 { -@@ -755,13 +874,43 @@ sdhc_1: mmc@4744000 { - resets = <&gcc GCC_SDCC1_BCR>; - - power-domains = <&rpmpd QCM2290_VDDCX>; -+ operating-points-v2 = <&sdhc1_opp_table>; - iommus = <&apps_smmu 0xc0 0x0>; -+ interconnects = <&system_noc MASTER_SDCC_1 0 &bimc SLAVE_EBI1 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_1 0>; -+ interconnect-names = "sdhc-ddr", -+ "cpu-sdhc"; - - qcom,dll-config = <0x000f642c>; - qcom,ddr-config = <0x80040868>; - bus-width = <8>; - - status = "disabled"; -+ -+ sdhc1_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-100000000 { -+ opp-hz = /bits/ 64 <100000000>; -+ required-opps = <&rpmpd_opp_low_svs>; -+ opp-peak-kBps = <250000 133320>; -+ opp-avg-kBps = <102400 65000>; -+ }; -+ -+ opp-192000000 { -+ opp-hz = /bits/ 64 <192000000>; -+ required-opps = <&rpmpd_opp_low_svs>; -+ opp-peak-kBps = <800000 300000>; -+ opp-avg-kBps = <204800 200000>; -+ }; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ required-opps = <&rpmpd_opp_svs_plus>; -+ opp-peak-kBps = <800000 300000>; -+ opp-avg-kBps = <204800 200000>; -+ }; -+ }; - }; - - sdhc_2: mmc@4784000 { -@@ -785,6 +934,10 @@ sdhc_2: mmc@4784000 { - power-domains = <&rpmpd QCM2290_VDDCX>; - operating-points-v2 = <&sdhc2_opp_table>; - iommus = <&apps_smmu 0xa0 0x0>; -+ interconnects = <&system_noc MASTER_SDCC_2 0 &bimc SLAVE_EBI1 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; -+ interconnect-names = "sdhc-ddr", -+ "cpu-sdhc"; - - qcom,dll-config = <0x0007642c>; - qcom,ddr-config = <0x80040868>; -@@ -798,11 +951,15 @@ sdhc2_opp_table: opp-table { - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmpd_opp_low_svs>; -+ opp-peak-kBps = <250000 133320>; -+ opp-avg-kBps = <261438 150000>; - }; - - opp-202000000 { - opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmpd_opp_svs_plus>; -+ opp-peak-kBps = <800000 300000>; -+ opp-avg-kBps = <261438 300000>; - }; - }; - }; -@@ -850,6 +1007,12 @@ i2c0: i2c@4a80000 { - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, - <&gpi_dma0 1 0 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI1 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -866,6 +1029,10 @@ spi0: spi@4a80000 { - dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, - <&gpi_dma0 1 0 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc MASTER_APPSS_PROC 0>; -+ interconnect-names = "qup-core", -+ "qup-config"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -879,6 +1046,10 @@ uart0: serial@4a80000 { - clock-names = "se"; - pinctrl-0 = <&qup_uart0_default>; - pinctrl-names = "default"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc MASTER_APPSS_PROC 0>; -+ interconnect-names = "qup-core", -+ "qup-config"; - status = "disabled"; - }; - -@@ -893,6 +1064,12 @@ i2c1: i2c@4a84000 { - dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI1 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -909,6 +1086,10 @@ spi1: spi@4a84000 { - dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, - <&gpi_dma0 1 1 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc MASTER_APPSS_PROC 0>; -+ interconnect-names = "qup-core", -+ "qup-config"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -925,6 +1106,12 @@ i2c2: i2c@4a88000 { - dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI1 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -941,6 +1128,10 @@ spi2: spi@4a88000 { - dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc MASTER_APPSS_PROC 0>; -+ interconnect-names = "qup-core", -+ "qup-config"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -957,6 +1148,12 @@ i2c3: i2c@4a8c000 { - dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI1 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -973,6 +1170,10 @@ spi3: spi@4a8c000 { - dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, - <&gpi_dma0 1 3 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc MASTER_APPSS_PROC 0>; -+ interconnect-names = "qup-core", -+ "qup-config"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -989,6 +1190,12 @@ i2c4: i2c@4a90000 { - dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, - <&gpi_dma0 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI1 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1005,6 +1212,10 @@ spi4: spi@4a90000 { - dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, - <&gpi_dma0 1 4 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc MASTER_APPSS_PROC 0>; -+ interconnect-names = "qup-core", -+ "qup-config"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1018,6 +1229,10 @@ uart4: serial@4a90000 { - clock-names = "se"; - pinctrl-0 = <&qup_uart4_default>; - pinctrl-names = "default"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc MASTER_APPSS_PROC 0>; -+ interconnect-names = "qup-core", -+ "qup-config"; - status = "disabled"; - }; - -@@ -1032,6 +1247,12 @@ i2c5: i2c@4a94000 { - dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, - <&gpi_dma0 1 5 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI1 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1048,6 +1269,10 @@ spi5: spi@4a94000 { - dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, - <&gpi_dma0 1 5 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc MASTER_APPSS_PROC 0>; -+ interconnect-names = "qup-core", -+ "qup-config"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1057,9 +1282,10 @@ spi5: spi@4a94000 { - usb: usb@4ef8800 { - compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; - reg = <0x0 0x04ef8800 0x0 0x400>; -- interrupts = , -- ; -- interrupt-names = "hs_phy_irq", "ss_phy_irq"; -+ interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, -+ <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "hs_phy_irq", -+ "ss_phy_irq"; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, -@@ -1080,6 +1306,11 @@ usb: usb@4ef8800 { - - resets = <&gcc GCC_USB30_PRIM_BCR>; - power-domains = <&gcc GCC_USB30_PRIM_GDSC>; -+ /* TODO: USB<->IPA path */ -+ interconnects = <&system_noc MASTER_USB3_0 0 &bimc SLAVE_EBI1 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; -+ interconnect-names = "usb-ddr", -+ "apps-usb"; - wakeup-source; - - #address-cells = <2>; -@@ -1105,6 +1336,223 @@ usb_dwc3: usb@4e00000 { - }; - }; - -+ mdss: display-subsystem@5e00000 { -+ compatible = "qcom,qcm2290-mdss"; -+ reg = <0x0 0x05e00000 0x0 0x1000>; -+ reg-names = "mdss"; -+ interrupts = ; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ -+ clocks = <&gcc GCC_DISP_AHB_CLK>, -+ <&gcc GCC_DISP_HF_AXI_CLK>, -+ <&dispcc DISP_CC_MDSS_MDP_CLK>; -+ clock-names = "iface", -+ "bus", -+ "core"; -+ -+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; -+ -+ power-domains = <&dispcc MDSS_GDSC>; -+ -+ iommus = <&apps_smmu 0x420 0x2>, -+ <&apps_smmu 0x421 0x0>; -+ interconnects = <&mmrt_virt MASTER_MDP0 0 &bimc SLAVE_EBI1 0>, -+ <&bimc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>; -+ interconnect-names = "mdp0-mem", -+ "cpu-cfg"; -+ -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ status = "disabled"; -+ -+ mdp: display-controller@5e01000 { -+ compatible = "qcom,qcm2290-dpu"; -+ reg = <0x0 0x05e01000 0x0 0x8f000>, -+ <0x0 0x05eb0000 0x0 0x2008>; -+ reg-names = "mdp", -+ "vbif"; -+ -+ interrupt-parent = <&mdss>; -+ interrupts = <0>; -+ -+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>, -+ <&dispcc DISP_CC_MDSS_AHB_CLK>, -+ <&dispcc DISP_CC_MDSS_MDP_CLK>, -+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, -+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; -+ clock-names = "bus", -+ "iface", -+ "core", -+ "lut", -+ "vsync"; -+ -+ operating-points-v2 = <&mdp_opp_table>; -+ power-domains = <&rpmpd QCM2290_VDDCX>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ dpu_intf1_out: endpoint { -+ remote-endpoint = <&mdss_dsi0_in>; -+ }; -+ }; -+ }; -+ -+ mdp_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-19200000 { -+ opp-hz = /bits/ 64 <19200000>; -+ required-opps = <&rpmpd_opp_min_svs>; -+ }; -+ -+ opp-192000000 { -+ opp-hz = /bits/ 64 <192000000>; -+ required-opps = <&rpmpd_opp_low_svs>; -+ }; -+ -+ opp-256000000 { -+ opp-hz = /bits/ 64 <256000000>; -+ required-opps = <&rpmpd_opp_svs>; -+ }; -+ -+ opp-307200000 { -+ opp-hz = /bits/ 64 <307200000>; -+ required-opps = <&rpmpd_opp_svs_plus>; -+ }; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ required-opps = <&rpmpd_opp_nom>; -+ }; -+ }; -+ }; -+ -+ mdss_dsi0: dsi@5e94000 { -+ compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; -+ reg = <0x0 0x05e94000 0x0 0x400>; -+ reg-names = "dsi_ctrl"; -+ -+ interrupt-parent = <&mdss>; -+ interrupts = <4>; -+ -+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, -+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, -+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>, -+ <&dispcc DISP_CC_MDSS_ESC0_CLK>, -+ <&dispcc DISP_CC_MDSS_AHB_CLK>, -+ <&gcc GCC_DISP_HF_AXI_CLK>; -+ clock-names = "byte", -+ "byte_intf", -+ "pixel", -+ "core", -+ "iface", -+ "bus"; -+ -+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, -+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; -+ assigned-clock-parents = <&mdss_dsi0_phy 0>, -+ <&mdss_dsi0_phy 1>; -+ -+ operating-points-v2 = <&dsi_opp_table>; -+ power-domains = <&rpmpd QCM2290_VDDCX>; -+ phys = <&mdss_dsi0_phy>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "disabled"; -+ -+ dsi_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-19200000 { -+ opp-hz = /bits/ 64 <19200000>; -+ required-opps = <&rpmpd_opp_min_svs>; -+ }; -+ -+ opp-164000000 { -+ opp-hz = /bits/ 64 <164000000>; -+ required-opps = <&rpmpd_opp_low_svs>; -+ }; -+ -+ opp-187500000 { -+ opp-hz = /bits/ 64 <187500000>; -+ required-opps = <&rpmpd_opp_svs>; -+ }; -+ }; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ mdss_dsi0_in: endpoint { -+ remote-endpoint = <&dpu_intf1_out>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ mdss_dsi0_out: endpoint { -+ }; -+ }; -+ }; -+ }; -+ -+ mdss_dsi0_phy: phy@5e94400 { -+ compatible = "qcom,dsi-phy-14nm-2290"; -+ reg = <0x0 0x05e94400 0x0 0x100>, -+ <0x0 0x05e94500 0x0 0x300>, -+ <0x0 0x05e94800 0x0 0x188>; -+ reg-names = "dsi_phy", -+ "dsi_phy_lane", -+ "dsi_pll"; -+ -+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, -+ <&rpmcc RPM_SMD_XO_CLK_SRC>; -+ clock-names = "iface", -+ "ref"; -+ -+ power-domains = <&rpmpd QCM2290_VDDMX>; -+ required-opps = <&rpmpd_opp_nom>; -+ -+ #clock-cells = <1>; -+ #phy-cells = <0>; -+ -+ status = "disabled"; -+ }; -+ }; -+ -+ dispcc: clock-controller@5f00000 { -+ compatible = "qcom,qcm2290-dispcc"; -+ reg = <0x0 0x05f00000 0x0 0x20000>; -+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, -+ <&rpmcc RPM_SMD_XO_A_CLK_SRC>, -+ <&gcc GCC_DISP_GPLL0_CLK_SRC>, -+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, -+ <&mdss_dsi0_phy 0>, -+ <&mdss_dsi0_phy 1>; -+ clock-names = "bi_tcxo", -+ "bi_tcxo_ao", -+ "gcc_disp_gpll0_clk_src", -+ "gcc_disp_gpll0_div_clk_src", -+ "dsi0_phy_pll_out_byteclk", -+ "dsi0_phy_pll_out_dsiclk"; -+ #power-domain-cells = <1>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ - remoteproc_mpss: remoteproc@6080000 { - compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; - reg = <0x0 0x06080000 0x0 0x100>; -diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts -index fd38a6278f2..6352b4976b9 100644 ---- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts -+++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts -@@ -23,6 +23,14 @@ chosen { - stdout-path = "serial0:115200n8"; - }; - -+ clocks { -+ clk40M: can-clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <40000000>; -+ #clock-cells = <0>; -+ }; -+ }; -+ - gpio-keys { - compatible = "gpio-keys"; - label = "gpio-keys"; -@@ -72,6 +80,49 @@ led-wlan { - }; - }; - -+ hdmi-connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con: endpoint { -+ remote-endpoint = <<9611_out>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-bt { -+ label = "blue:bt"; -+ function = LED_FUNCTION_BLUETOOTH; -+ color = ; -+ gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "bluetooth-power"; -+ default-state = "off"; -+ }; -+ -+ led-user0 { -+ label = "green:user0"; -+ function = LED_FUNCTION_INDICATOR; -+ color = ; -+ gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "none"; -+ default-state = "off"; -+ panic-indicator; -+ }; -+ -+ led-wlan { -+ label = "yellow:wlan"; -+ function = LED_FUNCTION_WLAN; -+ color = ; -+ gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "phy0tx"; -+ default-state = "off"; -+ }; -+ }; -+ - vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { - compatible = "regulator-fixed"; - regulator-name = "VREG_HDMI_OUT_1P2"; -@@ -158,6 +209,68 @@ vph_pwr: regulator-vph-pwr { - }; - }; - -+&gpi_dma0 { -+ status = "okay"; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+ lt9611_codec: hdmi-bridge@2b { -+ compatible = "lontium,lt9611uxc"; -+ reg = <0x2b>; -+ interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; -+ reset-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; -+ -+ vdd-supply = <&vreg_hdmi_out_1p2>; -+ vcc-supply = <<9611_3v3>; -+ -+ pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; -+ pinctrl-names = "default"; -+ #sound-dai-cells = <1>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ lt9611_a: endpoint { -+ remote-endpoint = <&mdss_dsi0_out>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ -+ lt9611_out: endpoint { -+ remote-endpoint = <&hdmi_con>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&mdss { -+ status = "okay"; -+}; -+ -+&mdss_dsi0 { -+ vdda-supply = <&pm2250_l5>; -+ status = "okay"; -+}; -+ -+&mdss_dsi0_out { -+ remote-endpoint = <<9611_a>; -+ data-lanes = <0 1 2 3>; -+}; -+ -+&mdss_dsi0_phy { -+ status = "okay"; -+}; -+ - &pm2250_resin { - linux,code = ; - status = "okay"; -@@ -376,7 +489,34 @@ &sdhc_2 { - status = "okay"; - }; - -+&spi5 { -+ status = "okay"; -+ -+ can@0 { -+ compatible = "microchip,mcp2518fd"; -+ reg = <0>; -+ interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>; -+ clocks = <&clk40M>; -+ spi-max-frequency = <10000000>; -+ vdd-supply = <&vdc_5v>; -+ xceiver-supply = <&vdc_5v>; -+ }; -+}; -+ - &tlmm { -+ lt9611_rst_pin: lt9611-rst-state { -+ pins = "gpio41"; -+ function = "gpio"; -+ input-disable; -+ output-high; -+ }; -+ -+ lt9611_irq_pin: lt9611-irq-state { -+ pins = "gpio46"; -+ function = "gpio"; -+ bias-disable; -+ }; -+ - sd_det_in_on: sd-det-in-on-state { - pins = "gpio88"; - function = "gpio"; -@@ -409,6 +549,10 @@ &usb { - status = "okay"; - }; - -+&usb_dwc3 { -+ dr_mode = "host"; -+}; -+ - &usb_qmpphy { - vdda-phy-supply = <&pm2250_l12>; - vdda-pll-supply = <&pm2250_l13>; -@@ -431,6 +575,7 @@ &wifi { - vdd-1.8-xo-supply = <&pm2250_l13>; - vdd-1.3-rfa-supply = <&pm2250_l10>; - vdd-3.3-ch0-supply = <&pm2250_l22>; -+ qcom,ath10k-calibration-variant = "Thundercomm_RB1"; - status = "okay"; - }; - -diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts -index 9738c0dacd5..8b3e8200ea5 100644 ---- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts -+++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts -@@ -280,6 +280,12 @@ &remoteproc_cdsp { - status = "okay"; - }; - -+&remoteproc_mpss { -+ firmware-name = "qcom/qrb4210/modem.mbn"; -+ -+ status = "okay"; -+}; -+ - &rpm_requests { - regulators { - compatible = "qcom,rpm-pm6125-regulators"; -@@ -346,8 +352,8 @@ vreg_l7a_1p256: l7 { - }; - - vreg_l8a_0p664: l8 { -- regulator-min-microvolt = <400000>; -- regulator-max-microvolt = <728000>; -+ regulator-min-microvolt = <640000>; -+ regulator-max-microvolt = <640000>; - }; - - vreg_l9a_1p8: l9 { -@@ -424,8 +430,8 @@ vreg_l22a_2p96: l22 { - }; - - vreg_l23a_3p3: l23 { -- regulator-min-microvolt = <3200000>; -- regulator-max-microvolt = <3400000>; -+ regulator-min-microvolt = <3312000>; -+ regulator-max-microvolt = <3312000>; - }; - - vreg_l24a_2p96: l24 { -@@ -518,6 +524,7 @@ &usb { - - &usb_dwc3 { - maximum-speed = "super-speed"; -+ dr_mode = "host"; - }; - - &usb_hsphy { -@@ -535,6 +542,15 @@ &usb_qmpphy { - status = "okay"; - }; - -+&wifi { -+ vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>; -+ vdd-1.8-xo-supply = <&vreg_l16a_1p3>; -+ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; -+ vdd-3.3-ch0-supply = <&vreg_l23a_3p3>; -+ qcom,ath10k-calibration-variant = "Thundercomm_RB2"; -+ status = "okay"; -+}; -+ - &xo_board { - clock-frequency = <19200000>; - }; -diff --git a/arch/arm64/boot/dts/qcom/sc7180-tcl-b220g.dts b/arch/arm64/boot/dts/qcom/sc7180-tcl-b220g.dts -new file mode 100644 -index 00000000000..a22062a9fc8 ---- /dev/null -+++ b/arch/arm64/boot/dts/qcom/sc7180-tcl-b220g.dts -@@ -0,0 +1,639 @@ -+// SPDX-License-Identifier: BSD-3-Clause -+ -+/dts-v1/; -+ -+#include -+#include -+ -+#include "sc7180.dtsi" -+ -+#include "pm6150.dtsi" -+#include "pm6150l.dtsi" -+ -+/delete-node/ &tz_mem; -+/delete-node/ &ipa_fw_mem; -+ -+/ { -+ model = "TCL Book 14 Go"; -+ compatible = "tcl,b220g", "qcom,sc7180"; -+ chassis-type = "laptop"; -+ -+ aliases { -+ bluetooth0 = &bluetooth; -+ hsuart0 = &uart3; -+ serial0 = &uart8; -+ wifi0 = &wifi; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ reserved-memory { -+ zap_mem: zap-shader@80840000 { -+ reg = <0x0 0x80840000 0 0x2000>; -+ no-map; -+ }; -+ -+ venus_mem: venus@85b00000 { -+ reg = <0x0 0x85b00000 0 0x500000>; -+ no-map; -+ }; -+ -+ mpss_mem: mpss@86000000 { -+ reg = <0x0 0x86000000 0x0 0x2000000>; -+ no-map; -+ }; -+ -+ adsp_mem: adsp@8e400000 { -+ reg = <0x0 0x8e400000 0x0 0x2800000>; -+ no-map; -+ }; -+ -+ wlan_mem: wlan@93900000 { -+ reg = <0x0 0x93900000 0x0 0x200000>; -+ no-map; -+ }; -+ // zap_mem: zap-shader@80840000 { -+ // reg = <0x0 0x80840000 0 0x2000>; -+ // no-map; -+ // }; -+ -+ // venus_mem: venus@85b00000 { -+ // reg = <0x0 0x85b00000 0 0x500000>; -+ // no-map; -+ // }; -+ -+ // mpss_mem: mpss@86000000 { -+ // reg = <0x0 0x86000000 0x0 0x2000000>; -+ // no-map; -+ // }; -+ -+ // adsp_mem: adsp@8be00000 { -+ // reg = <0x0 0x8be00000 0x0 0x1a00000>; -+ // no-map; -+ // }; -+ -+ // cdsp_mem: cdsp@98900000 { -+ // reg = <0x0 0x98900000 0x0 0x800000>; -+ // no-map; -+ // }; -+ -+ // slpi_mem: slpi@93700000 { -+ // reg = <0x0 0x93700000 0x0 0x1400000>; -+ // no-map; -+ // }; -+ -+ // wlan_mem: wlan@93900000 { -+ // reg = <0x0 0x93900000 0x0 0x200000>; -+ // no-map; -+ // }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+ /* embedded-controller@76 */ -+}; -+ -+&i2c4 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+ /* -+ * NOTE: DSDT defines two possible touchpads, other one is -+ * -+ * reg = <0x15>; -+ * hid-descr-addr = <0x1>; -+ */ -+ -+ touchpad@2c { -+ compatible = "hid-over-i2c"; -+ reg = <0x2c>; -+ hid-descr-addr = <0x20>; -+ -+ //vdd-supply = <®_tp_3p3>; -+ -+ interrupts-extended = <&tlmm 94 IRQ_TYPE_LEVEL_LOW>; -+ -+ // pinctrl-0 = <&hid_touchpad_default>; -+ // pinctrl-names = "default"; -+ -+ wakeup-source; -+ }; -+ -+ keyboard@3a { -+ compatible = "hid-over-i2c"; -+ reg = <0x3a>; -+ hid-descr-addr = <0x1>; -+ -+ interrupts-extended = <&tlmm 33 IRQ_TYPE_LEVEL_LOW>; -+ -+ // pinctrl-0 = <&hid_keyboard_default>; -+ // pinctrl-names = "default"; -+ -+ wakeup-source; -+ }; -+}; -+ -+&i2c9 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+}; -+ -+&i2c10 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+}; -+ -+&gpu { -+ status = "okay"; -+ -+ zap-shader { -+ memory-region = <&zap_mem>; -+ firmware-name = "qcom/sc7180/acer/aspire1/qcdxkmsuc7180.mbn"; -+ }; -+}; -+ -+// &mdss { -+// status = "okay"; -+// }; -+ -+// &mdss_dsi0 { -+// vdda-supply = <&vreg_l3c_1p2>; -+// status = "okay"; -+// }; -+ -+// &mdss_dsi0_out { -+// remote-endpoint = <&sn65dsi86_in>; -+// data-lanes = <0 1 2 3>; -+// }; -+ -+// &mdss_dsi0_phy { -+// vdds-supply = <&vreg_l4a_0p8>; -+// status = "okay"; -+// }; -+ -+&pm6150_adc { -+ channel@4e { -+ reg = ; -+ qcom,ratiometric; -+ qcom,hw-settle-time = <200>; -+ label = "thermistor"; -+ }; -+ -+ channel@4f { -+ reg = ; -+ qcom,ratiometric; -+ qcom,hw-settle-time = <200>; -+ label = "charger_thermistor"; -+ }; -+}; -+ -+&pm6150_adc_tm { -+ status = "okay"; -+ -+ charger-thermistor@0 { -+ reg = <0>; -+ io-channels = <&pm6150_adc ADC5_AMUX_THM3_100K_PU>; -+ qcom,ratiometric; -+ qcom,hw-settle-time-us = <200>; -+ }; -+ -+ thermistor@1 { -+ reg = <1>; -+ io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>; -+ qcom,ratiometric; -+ qcom,hw-settle-time-us = <200>; -+ }; -+}; -+ -+&pm6150_pon { -+ status = "disabled"; -+}; -+ -+&qupv3_id_0 { -+ status = "okay"; -+}; -+ -+&qupv3_id_1 { -+ status = "okay"; -+}; -+ -+&remoteproc_mpss { -+ firmware-name = "qcom/sc7180/acer/aspire1/qcmpss7180_nm.mbn"; -+ status = "okay"; -+}; -+ -+&sdhc_1 { -+ pinctrl-0 = <&sdc1_default>; -+ pinctrl-1 = <&sdc1_sleep>; -+ pinctrl-names = "default", "sleep"; -+ vmmc-supply = <&vreg_l19a_2p9>; -+ vqmmc-supply = <&vreg_l12a_1p8>; -+ -+ status = "okay"; -+}; -+ -+&uart3 { -+ /delete-property/interrupts; -+ interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, -+ <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; -+ -+ pinctrl-1 = <&qup_uart3_sleep>; -+ pinctrl-names = "default", "sleep"; -+ -+ status = "okay"; -+ -+ bluetooth: bluetooth { -+ compatible = "qcom,wcn3991-bt"; -+ vddio-supply = <&vreg_l10a_1p8>; -+ vddxo-supply = <&vreg_l1c_1p8>; -+ vddrf-supply = <&vreg_l2c_1p3>; -+ vddch0-supply = <&vreg_l10c_3p3>; -+ max-speed = <3200000>; -+ }; -+}; -+ -+&uart8 { -+ status = "okay"; -+}; -+ -+&ufs_mem_hc { -+ status = "okay"; -+ -+ reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; -+ -+ // vcc-supply = <&vreg_l20a_2p95>; -+ // vcc-max-microamp = <600000>; -+}; -+ -+&ufs_mem_phy { -+ status = "okay"; -+ -+ vdda-phy-supply = <&vdd_ufs1_core>; -+ vdda-pll-supply = <&vdd_ufs1_1p2>; -+}; -+ -+&usb_1 { -+ status = "okay"; -+}; -+ -+&usb_1_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usb_hub_2_x: hub@1 { -+ compatible = "usbbda,5411"; -+ reg = <1>; -+ peer-hub = <&usb_hub_3_x>; -+ }; -+ -+ usb_hub_3_x: hub@2 { -+ compatible = "usbbda,411"; -+ reg = <2>; -+ peer-hub = <&usb_hub_2_x>; -+ }; -+}; -+ -+&usb_1_hsphy { -+ vdd-supply = <&vreg_l4a_0p8>; -+ vdda-pll-supply = <&vreg_l11a_1p8>; -+ vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; -+ qcom,imp-res-offset-value = <8>; -+ qcom,preemphasis-level = ; -+ qcom,preemphasis-width = ; -+ qcom,bias-ctrl-value = <0x22>; -+ qcom,charge-ctrl-value = <3>; -+ qcom,hsdisc-trim-value = <0>; -+ -+ status = "okay"; -+}; -+ -+&usb_1_qmpphy { -+ vdda-phy-supply = <&vreg_l3c_1p2>; -+ vdda-pll-supply = <&vreg_l4a_0p8>; -+ -+ status = "okay"; -+}; -+ -+&venus { -+ firmware-name = "qcom/sc7180/acer/aspire1/qcvss7180.mbn"; -+}; -+ -+&wifi { -+ vdd-0.8-cx-mx-supply = <&vreg_l9a_0p6>; -+ vdd-1.8-xo-supply = <&vreg_l1c_1p8>; -+ vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; -+ vdd-3.3-ch0-supply = <&vreg_l10c_3p3>; -+ vdd-3.3-ch1-supply = <&vreg_l11c_3p3>; -+ -+ status = "okay"; -+}; -+ -+&apps_rsc { -+ regulators-0 { -+ compatible = "qcom,pm6150-rpmh-regulators"; -+ qcom,pmic-id = "a"; -+ -+ vreg_s1a_1p1: smps1 { -+ regulator-min-microvolt = <1128000>; -+ regulator-max-microvolt = <1128000>; -+ }; -+ -+ vdd_ufs1_core: -+ vreg_l4a_0p8: ldo4 { -+ regulator-min-microvolt = <824000>; -+ regulator-max-microvolt = <928000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l9a_0p6: ldo9 { -+ regulator-min-microvolt = <488000>; -+ regulator-max-microvolt = <800000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l10a_1p8: ldo10 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-initial-mode = ; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vreg_l11a_1p8: ldo11 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l12a_1p8: ldo12 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l13a_1p8: ldo13 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l14a_1p8: ldo14 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l15a_1p8: ldo15 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l16a_2p7: ldo16 { -+ regulator-min-microvolt = <2496000>; -+ regulator-max-microvolt = <3304000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l17a_3p0: ldo17 { -+ regulator-min-microvolt = <2920000>; -+ regulator-max-microvolt = <3232000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l18a_2p8: ldo18 { -+ regulator-min-microvolt = <2496000>; -+ regulator-max-microvolt = <3304000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l19a_2p9: ldo19 { -+ regulator-min-microvolt = <2960000>; -+ regulator-max-microvolt = <2960000>; -+ regulator-initial-mode = ; -+ }; -+ }; -+ -+ regulators-1 { -+ compatible = "qcom,pm6150l-rpmh-regulators"; -+ qcom,pmic-id = "c"; -+ -+ vreg_s8c_1p3: smps8 { -+ regulator-min-microvolt = <1120000>; -+ regulator-max-microvolt = <1408000>; -+ }; -+ -+ vreg_l1c_1p8: ldo1 { -+ regulator-min-microvolt = <1616000>; -+ regulator-max-microvolt = <1984000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l2c_1p3: ldo2 { -+ regulator-min-microvolt = <1168000>; -+ regulator-max-microvolt = <1304000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vdd_ufs1_1p2: -+ vreg_l3c_1p2: ldo3 { -+ regulator-min-microvolt = <1144000>; -+ regulator-max-microvolt = <1304000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l4c_1p8: ldo4 { -+ regulator-min-microvolt = <1648000>; -+ regulator-max-microvolt = <3304000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l5c_1p8: ldo5 { -+ regulator-min-microvolt = <1648000>; -+ regulator-max-microvolt = <3304000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l6c_2p9: ldo6 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <2950000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l7c_3p0: ldo7 { -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3312000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l8c_1p8: ldo8 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l9c_2p9: ldo9 { -+ regulator-min-microvolt = <2952000>; -+ regulator-max-microvolt = <2952000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l10c_3p3: ldo10 { -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_l11c_3p3: ldo11 { -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-initial-mode = ; -+ }; -+ -+ vreg_bob: bob { -+ regulator-min-microvolt = <3008000>; -+ regulator-max-microvolt = <3960000>; -+ regulator-initial-mode = ; -+ }; -+ }; -+}; -+ -+// &qup_i2c2_default { -+// drive-strength = <2>; -+ -+// /* Has external pullup */ -+// bias-disable; -+// }; -+ -+// &qup_i2c4_default { -+// drive-strength = <2>; -+ -+// /* Has external pullup */ -+// bias-disable; -+// }; -+ -+// &qup_i2c9_default { -+// drive-strength = <2>; -+ -+// /* Has external pullup */ -+// bias-disable; -+// }; -+ -+// &qup_i2c10_default { -+// drive-strength = <2>; -+ -+// /* Has external pullup */ -+// bias-disable; -+// }; -+ -+&tlmm { -+ /* -+ * The TZ seem to protect those because some boards can have -+ * fingerprint sensor connected to this range. Not connected -+ * on this board -+ */ -+ gpio-reserved-ranges = <58 5>; -+ -+ qup_uart3_sleep: qup-uart3-sleep-state { -+ cts-pins { -+ /* -+ * Configure a pull-down on CTS to match the pull of -+ * the Bluetooth module. -+ */ -+ pins = "gpio38"; -+ function = "gpio"; -+ bias-pull-down; -+ }; -+ -+ rts-pins { -+ /* -+ * Configure pull-down on RTS. As RTS is active low -+ * signal, pull it low to indicate the BT SoC that it -+ * can wakeup the system anytime from suspend state by -+ * pulling RX low (by sending wakeup bytes). -+ */ -+ pins = "gpio39"; -+ function = "gpio"; -+ bias-pull-down; -+ }; -+ -+ tx-pins { -+ /* -+ * Configure pull-up on TX when it isn't actively driven -+ * to prevent BT SoC from receiving garbage during sleep. -+ */ -+ pins = "gpio40"; -+ function = "gpio"; -+ bias-pull-up; -+ }; -+ -+ rx-pins { -+ /* -+ * Configure a pull-up on RX. This is needed to avoid -+ * garbage data when the TX pin of the Bluetooth module -+ * is floating which may cause spurious wakeups. -+ */ -+ pins = "gpio41"; -+ function = "gpio"; -+ bias-pull-up; -+ }; -+ }; -+ -+ sdc1_default: sdc1-default-state { -+ clk-pins { -+ pins = "sdc1_clk"; -+ drive-strength = <16>; -+ bias-disable; -+ }; -+ -+ cmd-pins { -+ pins = "sdc1_cmd"; -+ drive-strength = <16>; -+ bias-pull-up; -+ }; -+ -+ data-pins { -+ pins = "sdc1_data"; -+ drive-strength = <16>; -+ bias-pull-up; -+ }; -+ -+ rclk-pins { -+ pins = "sdc1_rclk"; -+ bias-pull-down; -+ }; -+ }; -+ -+ sdc1_sleep: sdc1-sleep-state { -+ clk-pins { -+ pins = "sdc1_clk"; -+ drive-strength = <2>; -+ bias-disable; -+ }; -+ -+ cmd-pins { -+ pins = "sdc1_cmd"; -+ drive-strength = <2>; -+ bias-pull-up; -+ }; -+ -+ data-pins { -+ pins = "sdc1_data"; -+ drive-strength = <2>; -+ bias-pull-up; -+ }; -+ -+ rclk-pins { -+ pins = "sdc1_rclk"; -+ bias-pull-down; -+ }; -+ }; -+}; -diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi -index c0365832c31..68ffd29f1a2 100644 ---- a/arch/arm64/boot/dts/qcom/sc7180.dtsi -+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi -@@ -1532,6 +1532,83 @@ mmss_noc: interconnect@1740000 { - qcom,bcm-voters = <&apps_bcm_voter>; - }; - -+ ufs_mem_hc: ufshc@1d84000 { -+ compatible = "qcom,sdm845-ufshc", "qcom,ufshc", -+ "jedec,ufs-2.0"; -+ reg = <0 0x01d84000 0 0x2500>, -+ <0 0x01d90000 0 0x8000>; -+ reg-names = "std", "ice"; -+ interrupts = ; -+ phys = <&ufs_mem_phy_lanes>; -+ phy-names = "ufsphy"; -+ lanes-per-direction = <2>; -+ power-domains = <&gcc UFS_PHY_GDSC>; -+ #reset-cells = <1>; -+ resets = <&gcc GCC_UFS_PHY_BCR>; -+ reset-names = "rst"; -+ -+ iommus = <&apps_smmu 0x100 0xf>; -+ -+ clock-names = -+ "core_clk", -+ "bus_aggr_clk", -+ "iface_clk", -+ "core_clk_unipro", -+ "ref_clk", -+ "tx_lane0_sync_clk", -+ "rx_lane0_sync_clk", -+ "ice_core_clk"; -+ clocks = -+ <&gcc GCC_UFS_PHY_AXI_CLK>, -+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, -+ <&gcc GCC_UFS_PHY_AHB_CLK>, -+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, -+ <&rpmhcc RPMH_CXO_CLK>, -+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, -+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, -+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; -+ freq-table-hz = -+ <50000000 200000000>, -+ <0 0>, -+ <0 0>, -+ <37500000 150000000>, -+ <0 0>, -+ <0 0>, -+ <0 0>, -+ <75000000 300000000>; -+ -+ interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, -+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; -+ interconnect-names = "ufs-ddr", "cpu-ufs"; -+ -+ status = "disabled"; -+ }; -+ -+ ufs_mem_phy: phy@1d87000 { -+ compatible = "qcom,sdm845-qmp-ufs-phy"; -+ reg = <0 0x01d87000 0 0x18c>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ clock-names = "ref", -+ "ref_aux"; -+ clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, -+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; -+ -+ resets = <&ufs_mem_hc 0>; -+ reset-names = "ufsphy"; -+ status = "disabled"; -+ -+ ufs_mem_phy_lanes: phy@1d87400 { -+ reg = <0 0x01d87400 0 0x108>, -+ <0 0x01d87600 0 0x1e0>, -+ <0 0x01d87c00 0 0x1dc>, -+ <0 0x01d87800 0 0x108>, -+ <0 0x01d87a00 0 0x1e0>; -+ #phy-cells = <0>; -+ }; -+ }; -+ - ipa: ipa@1e40000 { - compatible = "qcom,sc7180-ipa"; - diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts -index 7e7bf3fb3be..d4f6284694a 100644 +index ab622045651..914855f5a22 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -194,6 +194,7 @@ pcie0_3p3v_dual: vldo-3v3-regulator { @@ -2475,22 +664,19 @@ index 99dafc6716e..57ed447409d 100644 memory@f0800000 { reg = <0 0xf0800000 0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi -index b523b5fff70..2cd4567bc94 100644 +index e821103d49c..e92dbd92ecf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi -@@ -8,9 +8,11 @@ - /dts-v1/; - - #include -+#include +@@ -12,6 +12,8 @@ #include #include #include +#include ++#include #include "sdm845.dtsi" #include "sdm845-wcd9340.dtsi" -@@ -20,6 +22,41 @@ +@@ -21,6 +23,41 @@ /delete-node/ &rmtfs_mem; / { @@ -2532,7 +718,7 @@ index b523b5fff70..2cd4567bc94 100644 aliases { serial0 = &uart9; serial1 = &uart6; -@@ -252,7 +289,6 @@ vreg_l14a_1p88: ldo14 { +@@ -253,7 +290,6 @@ vreg_l14a_1p88: ldo14 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; @@ -2540,7 +726,7 @@ index b523b5fff70..2cd4567bc94 100644 }; vreg_l17a_1p3: ldo17 { -@@ -388,6 +424,8 @@ synaptics-rmi4-i2c@20 { +@@ -389,6 +425,8 @@ synaptics-rmi4-i2c@20 { syna,reset-delay-ms = <200>; syna,startup-delay-ms = <200>; @@ -2549,7 +735,7 @@ index b523b5fff70..2cd4567bc94 100644 rmi4-f01@1 { reg = <0x01>; syna,nosleep-mode = <1>; -@@ -396,7 +434,7 @@ rmi4-f01@1 { +@@ -397,7 +435,7 @@ rmi4-f01@1 { rmi4_f12: rmi4-f12@12 { reg = <0x12>; touchscreen-x-mm = <68>; @@ -2558,32 +744,10 @@ index b523b5fff70..2cd4567bc94 100644 syna,sensor-type = <1>; syna,rezero-wait-ms = <200>; }; -@@ -484,6 +522,46 @@ &pmi8998_charger { - status = "okay"; +@@ -507,6 +545,24 @@ led-1 { + }; }; -+&pmi8998_flash { -+ status = "okay"; -+ -+ led-0 { -+ function = LED_FUNCTION_FLASH; -+ color = ; -+ led-sources = <1>; -+ led-max-microamp = <500000>; -+ flash-max-microamp = <1500000>; -+ flash-max-timeout-us = <1280000>; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_FLASH; -+ color = ; -+ led-sources = <2>; -+ led-max-microamp = <500000>; -+ flash-max-microamp = <1500000>; -+ flash-max-timeout-us = <1280000>; -+ }; -+}; -+ +&pmi8998_haptics { + status = "okay"; + @@ -2605,7 +769,7 @@ index b523b5fff70..2cd4567bc94 100644 &q6afedai { qi2s@22 { reg = <22>; -@@ -603,6 +681,13 @@ cpu { +@@ -626,6 +682,13 @@ cpu { }; }; @@ -2619,7 +783,7 @@ index b523b5fff70..2cd4567bc94 100644 speaker_playback_dai: speaker-dai-link { link-name = "Speaker Playback"; cpu { -@@ -780,8 +865,9 @@ hall_sensor_default: hall-sensor-default-state { +@@ -803,8 +866,9 @@ hall_sensor_default: hall-sensor-default-state { bias-disable; }; @@ -2631,7 +795,7 @@ index b523b5fff70..2cd4567bc94 100644 function = "gpio"; drive-strength = <2>; bias-disable; -@@ -849,4 +935,5 @@ &wifi { +@@ -872,4 +936,5 @@ &wifi { vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; qcom,snoc-host-cap-8bit-quirk; @@ -3507,7 +1671,7 @@ index b02a1dc5fec..c4845b0e3b1 100644 compatible = "ramoops"; reg = <0x0 0xffc00000 0x0 0x100000>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi -index 93b1582e807..3b2177bb175 100644 +index 617b17b2d7d..3b2177bb175 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -7,6 +7,9 @@ @@ -3584,32 +1748,10 @@ index 93b1582e807..3b2177bb175 100644 &pm8998_gpios { vol_up_pin_a: vol-up-active-state { pins = "gpio6"; -@@ -355,6 +380,35 @@ &pmi8998_charger { - status = "okay"; +@@ -377,6 +402,13 @@ led-1 { + }; }; -+&pmi8998_flash { -+ status = "okay"; -+ -+ led-0 { -+ function = LED_FUNCTION_FLASH; -+ color = ; -+ led-sources = <1>; -+ led-max-microamp = <500000>; -+ flash-max-microamp = <1500000>; -+ flash-max-timeout-us = <1280000>; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_FLASH; -+ color = ; -+ led-sources = <2>; -+ led-max-microamp = <500000>; -+ flash-max-microamp = <1500000>; -+ flash-max-timeout-us = <1280000>; -+ }; -+}; -+ +&pmi8998_fg { + status = "okay"; + @@ -3620,7 +1762,7 @@ index 93b1582e807..3b2177bb175 100644 &pm8998_resin { linux,code = ; status = "okay"; -@@ -380,12 +434,37 @@ dai@1 { +@@ -402,12 +434,37 @@ dai@1 { dai@2 { reg = <2>; }; @@ -3658,7 +1800,7 @@ index 93b1582e807..3b2177bb175 100644 &sdhc_2 { status = "okay"; -@@ -414,21 +493,50 @@ &sound { +@@ -436,21 +493,50 @@ &sound { mm1-dai-link { link-name = "MultiMedia1"; cpu { @@ -3712,7 +1854,7 @@ index 93b1582e807..3b2177bb175 100644 }; }; -@@ -448,7 +556,7 @@ codec { +@@ -470,7 +556,7 @@ codec { }; slimcap-dai-link { @@ -3721,7 +1863,7 @@ index 93b1582e807..3b2177bb175 100644 cpu { sound-dai = <&q6afedai SLIMBUS_0_TX>; }; -@@ -458,7 +566,22 @@ platform { +@@ -480,7 +566,22 @@ platform { }; codec { @@ -3745,7 +1887,7 @@ index 93b1582e807..3b2177bb175 100644 }; }; }; -@@ -491,6 +614,37 @@ sdc2_card_det_n: sd-card-det-n-state { +@@ -513,6 +614,37 @@ sdc2_card_det_n: sd-card-det-n-state { function = "gpio"; bias-pull-up; }; @@ -3783,7 +1925,7 @@ index 93b1582e807..3b2177bb175 100644 }; &uart6 { -@@ -579,4 +733,7 @@ &wifi { +@@ -601,4 +733,7 @@ &wifi { vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; @@ -3850,7 +1992,7 @@ index e9427851eba..0ca1997f934 100644 + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi -index 9648505644f..fca4e070f12 100644 +index c2244824355..bedf09590a1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -888,6 +888,11 @@ mdata_mem: mpss-metadata { @@ -3898,7 +2040,7 @@ index 9648505644f..fca4e070f12 100644 }; fastrpc { -@@ -3353,8 +3384,8 @@ slpi_pas: remoteproc@5c00000 { +@@ -3366,8 +3397,8 @@ slpi_pas: remoteproc@5c00000 { qcom,qmp = <&aoss_qmp>; @@ -3909,41 +2051,31 @@ index 9648505644f..fca4e070f12 100644 power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; -@@ -4053,10 +4084,10 @@ usb_1: usb@a6f8800 { - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; +@@ -4433,6 +4464,8 @@ mdss: display-subsystem@ae00000 { -- interrupts = , -- , -- , -- ; -+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, -+ <&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, -+ <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, -+ <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - -@@ -4104,10 +4135,10 @@ usb_2: usb@a8f8800 { - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; - -- interrupts = , -- , -- , -- ; -+ interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, -+ <&intc GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, -+ <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, -+ <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + power-domains = <&dispcc MDSS_GDSC>; ++ //resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; ++ + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts -index 92a812b5f42..c54e7d3612f 100644 +index 47dc42f6e93..47a28baa0ec 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts -@@ -370,6 +370,33 @@ zap-shader { +@@ -37,6 +37,10 @@ aliases { + serial1 = &uart6; + }; + ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ + gpio-keys { + compatible = "gpio-keys"; + +@@ -370,6 +374,33 @@ zap-shader { &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -3977,7 +2109,7 @@ index 92a812b5f42..c54e7d3612f 100644 }; &i2c3 { -@@ -561,6 +588,11 @@ dai@2 { +@@ -567,6 +598,11 @@ dai@2 { }; }; @@ -3989,7 +2121,7 @@ index 92a812b5f42..c54e7d3612f 100644 &sound { compatible = "lenovo,yoga-c630-sndcard", "qcom,sdm845-sndcard"; model = "Lenovo-YOGA-C630-13Q50"; -@@ -688,6 +720,14 @@ mode_pin_active: mode-pin-state { +@@ -694,6 +730,14 @@ mode_pin_active: mode-pin-state { bias-disable; }; @@ -4005,7 +2137,7 @@ index 92a812b5f42..c54e7d3612f 100644 &uart6 { diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts -index 54383731600..fae9492b9ec 100644 +index 26217836c27..bec0033aeca 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -61,12 +61,6 @@ aliases { @@ -4043,411 +2175,12 @@ index da9f6fbe32f..89eda97daa5 100644 &cpu4_opp_table { cpu4_opp33: opp-2841600000 { opp-hz = /bits/ 64 <2841600000>; -diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi -index 839c6035124..258eebfbaba 100644 ---- a/arch/arm64/boot/dts/qcom/sm6115.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -264,6 +265,7 @@ firmware { - scm: scm { - compatible = "qcom,scm-sm6115", "qcom,scm"; - #reset-cells = <1>; -+ interconnects = <&system_noc MASTER_CRYPTO_CORE0 0 &bimc SLAVE_EBI_CH0 0>; - }; - }; - -@@ -859,6 +861,43 @@ usb_qmpphy: phy@1615000 { - status = "disabled"; - }; - -+ system_noc: interconnect@1880000 { -+ compatible = "qcom,sm6115-snoc"; -+ reg = <0x0 0x01880000 0x0 0x5f080>; -+ clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>, -+ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, -+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, -+ <&rpmcc RPM_SMD_IPA_CLK>; -+ clock-names = "cpu_axi", -+ "ufs_axi", -+ "usb_axi", -+ "ipa"; -+ #interconnect-cells = <2>; -+ -+ clk_virt: interconnect-clk { -+ compatible = "qcom,sm6115-clk-virt"; -+ #interconnect-cells = <2>; -+ }; -+ -+ mmrt_virt: interconnect-mmrt { -+ compatible = "qcom,sm6115-mmrt-virt"; -+ #interconnect-cells = <2>; -+ }; -+ -+ mmnrt_virt: interconnect-mmnrt { -+ compatible = "qcom,sm6115-mmnrt-virt"; -+ #interconnect-cells = <2>; -+ }; -+ }; -+ -+ config_noc: interconnect@1900000 { -+ compatible = "qcom,sm6115-cnoc"; -+ reg = <0x0 0x01900000 0x0 0x6200>; -+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; -+ clock-names = "usb_axi"; -+ #interconnect-cells = <2>; -+ }; -+ - qfprom@1b40000 { - compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; - reg = <0x0 0x01b40000 0x0 0x7000>; -@@ -883,6 +922,59 @@ rng: rng@1b53000 { - clock-names = "core"; - }; - -+ pmu@1b8e300 { -+ compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon"; -+ reg = <0x0 0x01b8e300 0x0 0x600>; -+ interrupts = ; -+ -+ operating-points-v2 = <&cpu_bwmon_opp_table>; -+ interconnects = <&bimc MASTER_AMPSS_M0 1 &bimc SLAVE_EBI_CH0 1>; -+ -+ cpu_bwmon_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-0 { -+ opp-peak-kBps = <(200 * 4 * 1000)>; -+ }; -+ -+ opp-1 { -+ opp-peak-kBps = <(300 * 4 * 1000)>; -+ }; -+ -+ opp-2 { -+ opp-peak-kBps = <(451 * 4 * 1000)>; -+ }; -+ -+ opp-3 { -+ opp-peak-kBps = <(547 * 4 * 1000)>; -+ }; -+ -+ opp-4 { -+ opp-peak-kBps = <(681 * 4 * 1000)>; -+ }; -+ -+ opp-5 { -+ opp-peak-kBps = <(768 * 4 * 1000)>; -+ }; -+ -+ opp-6 { -+ opp-peak-kBps = <(1017 * 4 * 1000)>; -+ }; -+ -+ opp-7 { -+ opp-peak-kBps = <(1353 * 4 * 1000)>; -+ }; -+ -+ opp-8 { -+ opp-peak-kBps = <(1555 * 4 * 1000)>; -+ }; -+ -+ opp-9 { -+ opp-peak-kBps = <(1804 * 4 * 1000)>; -+ }; -+ }; -+ }; -+ - spmi_bus: spmi@1c40000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x01c40000 0x0 0x1100>, -@@ -912,6 +1004,12 @@ tsens0: thermal-sensor@4411000 { - #thermal-sensor-cells = <1>; - }; - -+ bimc: interconnect@4480000 { -+ compatible = "qcom,sm6115-bimc"; -+ reg = <0x0 0x04480000 0x0 0x80000>; -+ #interconnect-cells = <2>; -+ }; -+ - rpm_msg_ram: sram@45f0000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x0 0x045f0000 0x0 0x7000>; -@@ -939,8 +1037,40 @@ sdhc_1: mmc@4744000 { - <&gcc GCC_SDCC1_ICE_CORE_CLK>; - clock-names = "iface", "core", "xo", "ice"; - -+ power-domains = <&rpmpd SM6115_VDDCX>; -+ operating-points-v2 = <&sdhc1_opp_table>; -+ interconnects = <&system_noc MASTER_SDCC_1 0 &bimc SLAVE_EBI_CH0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_1 0>; -+ interconnect-names = "sdhc-ddr", -+ "cpu-sdhc"; -+ - bus-width = <8>; - status = "disabled"; -+ -+ sdhc1_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-100000000 { -+ opp-hz = /bits/ 64 <100000000>; -+ required-opps = <&rpmpd_opp_low_svs>; -+ opp-peak-kBps = <250000 133320>; -+ opp-avg-kBps = <102400 65000>; -+ }; -+ -+ opp-192000000 { -+ opp-hz = /bits/ 64 <192000000>; -+ required-opps = <&rpmpd_opp_low_svs>; -+ opp-peak-kBps = <800000 300000>; -+ opp-avg-kBps = <204800 200000>; -+ }; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ required-opps = <&rpmpd_opp_svs_plus>; -+ opp-peak-kBps = <800000 300000>; -+ opp-avg-kBps = <204800 200000>; -+ }; -+ }; - }; - - sdhc_2: mmc@4784000 { -@@ -961,6 +1091,10 @@ sdhc_2: mmc@4784000 { - operating-points-v2 = <&sdhc2_opp_table>; - iommus = <&apps_smmu 0x00a0 0x0>; - resets = <&gcc GCC_SDCC2_BCR>; -+ interconnects = <&system_noc MASTER_SDCC_2 0 &bimc SLAVE_EBI_CH0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; -+ interconnect-names = "sdhc-ddr", -+ "cpu-sdhc"; - - bus-width = <4>; - qcom,dll-config = <0x0007642c>; -@@ -973,11 +1107,15 @@ sdhc2_opp_table: opp-table { - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmpd_opp_low_svs>; -+ opp-peak-kBps = <250000 133320>; -+ opp-avg-kBps = <261438 150000>; - }; - - opp-202000000 { - opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmpd_opp_nom>; -+ opp-peak-kBps = <800000 300000>; -+ opp-avg-kBps = <261438 300000>; - }; - }; - }; -@@ -1091,6 +1229,12 @@ i2c0: i2c@4a80000 { - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, - <&gpi_dma0 1 0 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1107,6 +1251,12 @@ spi0: spi@4a80000 { - dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, - <&gpi_dma0 1 0 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1123,6 +1273,12 @@ i2c1: i2c@4a84000 { - dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1139,6 +1295,12 @@ spi1: spi@4a84000 { - dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, - <&gpi_dma0 1 1 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1155,6 +1317,12 @@ i2c2: i2c@4a88000 { - dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1171,6 +1339,12 @@ spi2: spi@4a88000 { - dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1187,6 +1361,12 @@ i2c3: i2c@4a8c000 { - dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1203,6 +1383,12 @@ spi3: spi@4a8c000 { - dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, - <&gpi_dma0 1 3 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1219,6 +1405,12 @@ i2c4: i2c@4a90000 { - dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, - <&gpi_dma0 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1235,6 +1427,12 @@ spi4: spi@4a90000 { - dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, - <&gpi_dma0 1 4 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1246,6 +1444,12 @@ uart4: serial@4a90000 { - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - interrupts = ; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - status = "disabled"; - }; - -@@ -1260,6 +1464,12 @@ i2c5: i2c@4a94000 { - dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, - <&gpi_dma0 1 5 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1276,6 +1486,12 @@ spi5: spi@4a94000 { - dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, - <&gpi_dma0 1 5 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, -+ <&system_noc MASTER_QUP_0 0 &bimc SLAVE_EBI_CH0 0>; -+ interconnect-names = "qup-core", -+ "qup-config", -+ "qup-memory"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1307,6 +1523,12 @@ usb: usb@4ef8800 { - - resets = <&gcc GCC_USB30_PRIM_BCR>; - power-domains = <&gcc GCC_USB30_PRIM_GDSC>; -+ /* TODO: USB<->IPA path */ -+ interconnects = <&system_noc MASTER_USB3 0 &bimc SLAVE_EBI_CH0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; -+ interconnect-names = "usb-ddr", -+ "apps-usb"; -+ - qcom,select-utmi-as-pipe-clk; - status = "disabled"; - -@@ -1478,6 +1700,11 @@ mdss: display-subsystem@5e00000 { - iommus = <&apps_smmu 0x420 0x2>, - <&apps_smmu 0x421 0x0>; - -+ interconnects = <&mmrt_virt MASTER_MDP_PORT0 0 &bimc SLAVE_EBI_CH0 0>, -+ <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_DISPLAY_CFG 0>; -+ interconnect-names = "mdp0-mem", -+ "cpu-cfg"; -+ - #address-cells = <2>; - #size-cells = <2>; - ranges; diff --git a/arch/arm64/configs/sdm845.config b/arch/arm64/configs/sdm845.config new file mode 100644 -index 00000000000..8306c125202 +index 00000000000..cab91545104 --- /dev/null +++ b/arch/arm64/configs/sdm845.config -@@ -0,0 +1,1022 @@ +@@ -0,0 +1,1019 @@ +# Qualcomm Snapdragon 845 (SDM845) config fragment +CONFIG_LOCALVERSION="-sdm845" + @@ -4612,14 +2345,6 @@ index 00000000000..8306c125202 +CONFIG_INTERCONNECT_QCOM_SM8250=y +CONFIG_PHY_QCOM_QMP_USB=y + -+# SC7180 -+CONFIG_SC_GPUCC_7180=y -+CONFIG_SC_LPASS_CORECC_7180=y -+CONFIG_SC_MSS_7180=y -+CONFIG_SC_VIDEOCC_7180=y -+CONFIG_INTERCONNECT_QCOM_SC7180=y -+CONFIG_SC_DISPCC_7180=y -+ +# Qcom stuff +CONFIG_RPMSG_CHAR=y +CONFIG_QCOM_Q6V5_ADSP=m @@ -4720,11 +2445,13 @@ index 00000000000..8306c125202 +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_BINFMT_MISC=m ++# CONFIG_USB_MASS_STORAGE is not set + +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m ++CONFIG_NFT_COMPAT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m @@ -4736,11 +2463,14 @@ index 00000000000..8306c125202 +CONFIG_CIFS=y + +CONFIG_DRM_GUD=m ++CONFIG_UCLAMP_TASK=y ++CONFIG_UCLAMP_TASK_GROUP=y + +# pmos containers kconfig +CONFIG_CGROUP_FREEZER=y +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MARK=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_DUMMY=m +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_NET_CLS_CGROUP=m @@ -5470,88 +3200,23 @@ index 00000000000..8306c125202 +CONFIG_SM_DISPCC_8550=n +CONFIG_SM_GCC_8550=n +CONFIG_SM_TCSRCC_8550=n -diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c -index b5464199b63..32503ebb149 100644 ---- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c -+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c -@@ -1415,9 +1415,9 @@ static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - int ret; +diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c +index 735adfefc37..c900f949749 100644 +--- a/drivers/clk/qcom/dispcc-sdm845.c ++++ b/drivers/clk/qcom/dispcc-sdm845.c +@@ -814,6 +814,7 @@ static struct clk_regmap *disp_cc_sdm845_clocks[] = { - if (!pdata->pwm_enabled) { -- ret = pm_runtime_get_sync(pdata->dev); -+ ret = pm_runtime_get_sync(chip->dev); - if (ret < 0) { -- pm_runtime_put_sync(pdata->dev); -+ pm_runtime_put_sync(chip->dev); - return ret; - } - } -@@ -1433,7 +1433,7 @@ static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX), - SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX)); - if (ret) { -- dev_err(pdata->dev, "failed to mux in PWM function\n"); -+ dev_err(chip->dev, "failed to mux in PWM function\n"); - goto out; - } - } -@@ -1509,7 +1509,7 @@ static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + static const struct qcom_reset_map disp_cc_sdm845_resets[] = { + [DISP_CC_MDSS_RSCC_BCR] = { 0x5000 }, ++ [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, + }; - ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); - if (ret) { -- dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n"); -+ dev_err(chip->dev, "failed to update PWM_PRE_DIV\n"); - goto out; - } - -@@ -1521,7 +1521,7 @@ static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED); - ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv); - if (ret) { -- dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n"); -+ dev_err(chip->dev, "failed to update PWM_EN/PWM_INV\n"); - goto out; - } - -@@ -1529,7 +1529,7 @@ static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - out: - - if (!pdata->pwm_enabled) -- pm_runtime_put_sync(pdata->dev); -+ pm_runtime_put_sync(chip->dev); - - return ret; - } -@@ -1589,12 +1589,14 @@ static int ti_sn_pwm_probe(struct auxiliary_device *adev, - { - struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); - -- pdata->pchip.dev = pdata->dev; -+ pdata->pchip.dev = &adev->dev; - pdata->pchip.ops = &ti_sn_pwm_ops; - pdata->pchip.npwm = 1; - pdata->pchip.of_xlate = of_pwm_single_xlate; - pdata->pchip.of_pwm_n_cells = 1; - -+ devm_pm_runtime_enable(&adev->dev); -+ - return pwmchip_add(&pdata->pchip); - } - -@@ -1605,7 +1607,7 @@ static void ti_sn_pwm_remove(struct auxiliary_device *adev) - pwmchip_remove(&pdata->pchip); - - if (pdata->pwm_enabled) -- pm_runtime_put_sync(pdata->dev); -+ pm_runtime_put_sync(&adev->dev); - } - - static const struct auxiliary_device_id ti_sn_pwm_id_table[] = { + static struct gdsc *disp_cc_sdm845_gdscs[] = { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -index 7a0220d29a2..b35626b2df1 100644 +index c9c55e2ea58..e19f493cf7d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -@@ -2001,12 +2001,7 @@ static void a6xx_recover(struct msm_gpu *gpu) +@@ -2015,12 +2015,7 @@ static void a6xx_recover(struct msm_gpu *gpu) dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); dev_pm_genpd_synced_poweroff(gmu->cxpd); @@ -5565,7 +3230,7 @@ index 7a0220d29a2..b35626b2df1 100644 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); -@@ -2015,10 +2010,7 @@ static void a6xx_recover(struct msm_gpu *gpu) +@@ -2029,10 +2024,7 @@ static void a6xx_recover(struct msm_gpu *gpu) pm_runtime_use_autosuspend(&gpu->pdev->dev); @@ -5577,11 +3242,24 @@ index 7a0220d29a2..b35626b2df1 100644 gpu->active_submits = active_submits; mutex_unlock(&gpu->active_lock); +diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c +index 35423d10aaf..40d0991f645 100644 +--- a/drivers/gpu/drm/msm/msm_mdss.c ++++ b/drivers/gpu/drm/msm/msm_mdss.c +@@ -333,6 +333,8 @@ static int msm_mdss_reset(struct device *dev) + "failed to acquire mdss reset\n"); + } + ++ dev_info(dev, "toggle reset\n"); ++ + reset_control_assert(reset); + /* + * Tests indicate that reset has to be held for some period of time, diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig -index 99e14dc212e..99124320288 100644 +index 8f378374220..bf38b22f5ea 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig -@@ -398,6 +398,16 @@ config DRM_PANEL_NOVATEK_NT35560 +@@ -407,6 +407,16 @@ config DRM_PANEL_NOVATEK_NT35560 mode. This supports several panels such as Sony ACX424AKM and ACX424AKP. @@ -5598,7 +3276,7 @@ index 99e14dc212e..99124320288 100644 config DRM_PANEL_NOVATEK_NT35950 tristate "Novatek NT35950 DSI panel" depends on OF -@@ -644,16 +654,28 @@ config DRM_PANEL_SAMSUNG_S6E8AA0 +@@ -655,16 +665,28 @@ config DRM_PANEL_SAMSUNG_S6E8AA0 select VIDEOMODE_HELPERS config DRM_PANEL_SAMSUNG_SOFEF00 @@ -5630,7 +3308,7 @@ index 99e14dc212e..99124320288 100644 config DRM_PANEL_SEIKO_43WVF1G tristate "Seiko 43WVF1G panel" -@@ -825,6 +847,15 @@ config DRM_PANEL_VISIONOX_RM69299 +@@ -845,6 +867,15 @@ config DRM_PANEL_VISIONOX_RM69299 Say Y here if you want to enable support for Visionox RM69299 DSI Video Mode panel. @@ -5647,10 +3325,10 @@ index 99e14dc212e..99124320288 100644 tristate "Visionox VTDR6130" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile -index d10c3de51c6..9fd3ac441b3 100644 +index d94a644d0a6..8c0ed8b54bf 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile -@@ -37,6 +37,7 @@ obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o +@@ -38,6 +38,7 @@ obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35560) += panel-novatek-nt35560.o @@ -5658,7 +3336,7 @@ index d10c3de51c6..9fd3ac441b3 100644 obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35950) += panel-novatek-nt35950.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36523) += panel-novatek-nt36523.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36672A) += panel-novatek-nt36672a.o -@@ -66,6 +67,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI) += panel-samsung-s6e63m0-dsi.o +@@ -67,6 +68,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI) += panel-samsung-s6e63m0-dsi.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01) += panel-samsung-s6e88a0-ams452ef01.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0) += panel-samsung-s6e8aa0.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_SOFEF00) += panel-samsung-sofef00.o @@ -5666,7 +3344,7 @@ index d10c3de51c6..9fd3ac441b3 100644 obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o -@@ -84,6 +86,7 @@ obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o +@@ -86,6 +88,7 @@ obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o @@ -8635,7 +6313,7 @@ index 00000000000..aad8a0be679 +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Caleb Connolly "); diff --git a/drivers/input/rmi4/rmi_driver.c b/drivers/input/rmi4/rmi_driver.c -index 258d5fe3d39..2469d198485 100644 +index 42eaebb3bf5..18ecbe882eb 100644 --- a/drivers/input/rmi4/rmi_driver.c +++ b/drivers/input/rmi4/rmi_driver.c @@ -136,9 +136,14 @@ static int rmi_process_interrupt_requests(struct rmi_device *rmi_dev) @@ -8901,7 +6579,7 @@ index 1c6c6086c0e..2531c32d616 100644 #define RMI_REG_DESC_SUBPACKET_BITS (37 * BITS_PER_BYTE) diff --git a/drivers/input/rmi4/rmi_f01.c b/drivers/input/rmi4/rmi_f01.c -index d7603c50f86..4aee30d2dcd 100644 +index cc1d4b42464..a5b14e13838 100644 --- a/drivers/input/rmi4/rmi_f01.c +++ b/drivers/input/rmi4/rmi_f01.c @@ -250,6 +250,20 @@ static int rmi_f01_read_properties(struct rmi_device *rmi_dev, @@ -9119,7 +6797,7 @@ index 488adaca4dd..ad2ef14ae9f 100644 f55->cfg_num_rx_electrodes = f55->num_rx_electrodes; f55->cfg_num_tx_electrodes = f55->num_rx_electrodes; diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c -index 3e102bcc4a1..7955f69823d 100644 +index 2a1db113447..06ec0f2e18a 100644 --- a/drivers/input/touchscreen/edt-ft5x06.c +++ b/drivers/input/touchscreen/edt-ft5x06.c @@ -1462,6 +1462,10 @@ static const struct edt_i2c_chip_data edt_ft5x06_data = { @@ -9280,4350 +6958,11 @@ index 1a797e410a3..8baedae9361 100644 }, .probe = nvt_ts_probe, .id_table = nvt_ts_i2c_id, -diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig -index 62b516d38d0..d2a54c5ecd0 100644 ---- a/drivers/interconnect/qcom/Kconfig -+++ b/drivers/interconnect/qcom/Kconfig -@@ -191,6 +191,15 @@ config INTERCONNECT_QCOM_SDX75 - This is a driver for the Qualcomm Network-on-Chip on sdx75-based - platforms. - -+config INTERCONNECT_QCOM_SM6115 -+ tristate "Qualcomm SM6115 interconnect driver" -+ depends on INTERCONNECT_QCOM -+ depends on QCOM_SMD_RPM -+ select INTERCONNECT_QCOM_SMD_RPM -+ help -+ This is a driver for the Qualcomm Network-on-Chip on sm6115-based -+ platforms. -+ - config INTERCONNECT_QCOM_SM6350 - tristate "Qualcomm SM6350 interconnect driver" - depends on INTERCONNECT_QCOM_RPMH_POSSIBLE -diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile -index c5320e29396..7564042a30d 100644 ---- a/drivers/interconnect/qcom/Makefile -+++ b/drivers/interconnect/qcom/Makefile -@@ -24,6 +24,7 @@ qnoc-sdm845-objs := sdm845.o - qnoc-sdx55-objs := sdx55.o - qnoc-sdx65-objs := sdx65.o - qnoc-sdx75-objs := sdx75.o -+qnoc-sm6115-objs := sm6115.o - qnoc-sm6350-objs := sm6350.o - qnoc-sm8150-objs := sm8150.o - qnoc-sm8250-objs := sm8250.o -@@ -53,6 +54,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o - obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o - obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o - obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o -+obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) += qnoc-sm6115.o - obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o - obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o - obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o -diff --git a/drivers/interconnect/qcom/sm6115.c b/drivers/interconnect/qcom/sm6115.c -new file mode 100644 -index 00000000000..da8a85456f5 ---- /dev/null -+++ b/drivers/interconnect/qcom/sm6115.c -@@ -0,0 +1,1424 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (c) 2021, The Linux Foundation. All rights reserved. -+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. -+ * Copyright (c) 2023, Linaro Limited -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "icc-rpm.h" -+ -+static const char * const snoc_intf_clocks[] = { -+ "cpu_axi", -+ "ufs_axi", -+ "usb_axi", -+ "ipa", /* qxm_ipa */ -+}; -+ -+static const char * const cnoc_intf_clocks[] = { -+ "usb_axi", -+}; -+ -+enum { -+ SM6115_MASTER_AMPSS_M0, -+ SM6115_MASTER_ANOC_SNOC, -+ SM6115_MASTER_BIMC_SNOC, -+ SM6115_MASTER_CAMNOC_HF, -+ SM6115_MASTER_CAMNOC_SF, -+ SM6115_MASTER_CRYPTO_CORE0, -+ SM6115_MASTER_GRAPHICS_3D, -+ SM6115_MASTER_IPA, -+ SM6115_MASTER_MDP_PORT0, -+ SM6115_MASTER_PIMEM, -+ SM6115_MASTER_QDSS_BAM, -+ SM6115_MASTER_QDSS_DAP, -+ SM6115_MASTER_QDSS_ETR, -+ SM6115_MASTER_QPIC, -+ SM6115_MASTER_QUP_0, -+ SM6115_MASTER_QUP_CORE_0, -+ SM6115_MASTER_SDCC_1, -+ SM6115_MASTER_SDCC_2, -+ SM6115_MASTER_SNOC_BIMC_NRT, -+ SM6115_MASTER_SNOC_BIMC_RT, -+ SM6115_MASTER_SNOC_BIMC, -+ SM6115_MASTER_SNOC_CFG, -+ SM6115_MASTER_SNOC_CNOC, -+ SM6115_MASTER_TCU_0, -+ SM6115_MASTER_TIC, -+ SM6115_MASTER_USB3, -+ SM6115_MASTER_VIDEO_P0, -+ SM6115_MASTER_VIDEO_PROC, -+ -+ SM6115_SLAVE_AHB2PHY_USB, -+ SM6115_SLAVE_ANOC_SNOC, -+ SM6115_SLAVE_APPSS, -+ SM6115_SLAVE_APSS_THROTTLE_CFG, -+ SM6115_SLAVE_BIMC_CFG, -+ SM6115_SLAVE_BIMC_SNOC, -+ SM6115_SLAVE_BOOT_ROM, -+ SM6115_SLAVE_CAMERA_CFG, -+ SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, -+ SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, -+ SM6115_SLAVE_CLK_CTL, -+ SM6115_SLAVE_CNOC_MSS, -+ SM6115_SLAVE_CRYPTO_0_CFG, -+ SM6115_SLAVE_DCC_CFG, -+ SM6115_SLAVE_DDR_PHY_CFG, -+ SM6115_SLAVE_DDR_SS_CFG, -+ SM6115_SLAVE_DISPLAY_CFG, -+ SM6115_SLAVE_DISPLAY_THROTTLE_CFG, -+ SM6115_SLAVE_EBI_CH0, -+ SM6115_SLAVE_GPU_CFG, -+ SM6115_SLAVE_GPU_THROTTLE_CFG, -+ SM6115_SLAVE_HWKM_CORE, -+ SM6115_SLAVE_IMEM_CFG, -+ SM6115_SLAVE_IPA_CFG, -+ SM6115_SLAVE_LPASS, -+ SM6115_SLAVE_MAPSS, -+ SM6115_SLAVE_MDSP_MPU_CFG, -+ SM6115_SLAVE_MESSAGE_RAM, -+ SM6115_SLAVE_OCIMEM, -+ SM6115_SLAVE_PDM, -+ SM6115_SLAVE_PIMEM_CFG, -+ SM6115_SLAVE_PIMEM, -+ SM6115_SLAVE_PKA_CORE, -+ SM6115_SLAVE_PMIC_ARB, -+ SM6115_SLAVE_QDSS_CFG, -+ SM6115_SLAVE_QDSS_STM, -+ SM6115_SLAVE_QM_CFG, -+ SM6115_SLAVE_QM_MPU_CFG, -+ SM6115_SLAVE_QPIC, -+ SM6115_SLAVE_QUP_0, -+ SM6115_SLAVE_QUP_CORE_0, -+ SM6115_SLAVE_RBCPR_CX_CFG, -+ SM6115_SLAVE_RBCPR_MX_CFG, -+ SM6115_SLAVE_RPM, -+ SM6115_SLAVE_SDCC_1, -+ SM6115_SLAVE_SDCC_2, -+ SM6115_SLAVE_SECURITY, -+ SM6115_SLAVE_SERVICE_CNOC, -+ SM6115_SLAVE_SERVICE_SNOC, -+ SM6115_SLAVE_SNOC_BIMC_NRT, -+ SM6115_SLAVE_SNOC_BIMC_RT, -+ SM6115_SLAVE_SNOC_BIMC, -+ SM6115_SLAVE_SNOC_CFG, -+ SM6115_SLAVE_SNOC_CNOC, -+ SM6115_SLAVE_TCSR, -+ SM6115_SLAVE_TCU, -+ SM6115_SLAVE_TLMM, -+ SM6115_SLAVE_USB3, -+ SM6115_SLAVE_VENUS_CFG, -+ SM6115_SLAVE_VENUS_THROTTLE_CFG, -+ SM6115_SLAVE_VSENSE_CTRL_CFG, -+}; -+ -+static const u16 slv_ebi_slv_bimc_snoc_links[] = { -+ SM6115_SLAVE_EBI_CH0, -+ SM6115_SLAVE_BIMC_SNOC, -+}; -+ -+static struct qcom_icc_node apps_proc = { -+ .name = "apps_proc", -+ .id = SM6115_MASTER_AMPSS_M0, -+ .channels = 1, -+ .buswidth = 16, -+ .qos.qos_port = 0, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.prio_level = 0, -+ .qos.areq_prio = 0, -+ .mas_rpm_id = 0, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), -+ .links = slv_ebi_slv_bimc_snoc_links, -+}; -+ -+static const u16 link_slv_ebi[] = { -+ SM6115_SLAVE_EBI_CH0, -+}; -+ -+static struct qcom_icc_node mas_snoc_bimc_rt = { -+ .name = "mas_snoc_bimc_rt", -+ .id = SM6115_MASTER_SNOC_BIMC_RT, -+ .channels = 1, -+ .buswidth = 16, -+ .qos.qos_port = 2, -+ .qos.qos_mode = NOC_QOS_MODE_BYPASS, -+ .qos.areq_prio = 0, -+ .qos.prio_level = 0, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_ebi), -+ .links = link_slv_ebi, -+}; -+ -+static struct qcom_icc_node mas_snoc_bimc_nrt = { -+ .name = "mas_snoc_bimc_nrt", -+ .id = SM6115_MASTER_SNOC_BIMC_NRT, -+ .channels = 1, -+ .buswidth = 16, -+ .qos.qos_port = 3, -+ .qos.qos_mode = NOC_QOS_MODE_BYPASS, -+ .qos.areq_prio = 0, -+ .qos.prio_level = 0, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_ebi), -+ .links = link_slv_ebi, -+}; -+ -+static struct qcom_icc_node mas_snoc_bimc = { -+ .name = "mas_snoc_bimc", -+ .id = SM6115_MASTER_SNOC_BIMC, -+ .channels = 1, -+ .buswidth = 16, -+ .qos.qos_port = 6, -+ .qos.qos_mode = NOC_QOS_MODE_BYPASS, -+ .qos.areq_prio = 0, -+ .qos.prio_level = 0, -+ .mas_rpm_id = 3, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_ebi), -+ .links = link_slv_ebi, -+}; -+ -+static struct qcom_icc_node qnm_gpu = { -+ .name = "qnm_gpu", -+ .id = SM6115_MASTER_GRAPHICS_3D, -+ .channels = 1, -+ .buswidth = 32, -+ .qos.qos_port = 1, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.prio_level = 0, -+ .qos.areq_prio = 0, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), -+ .links = slv_ebi_slv_bimc_snoc_links, -+}; -+ -+static struct qcom_icc_node tcu_0 = { -+ .name = "tcu_0", -+ .id = SM6115_MASTER_TCU_0, -+ .channels = 1, -+ .buswidth = 8, -+ .qos.qos_port = 4, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.prio_level = 6, -+ .qos.areq_prio = 6, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), -+ .links = slv_ebi_slv_bimc_snoc_links, -+}; -+ -+static const u16 qup_core_0_links[] = { -+ SM6115_SLAVE_QUP_CORE_0, -+}; -+ -+static struct qcom_icc_node qup0_core_master = { -+ .name = "qup0_core_master", -+ .id = SM6115_MASTER_QUP_CORE_0, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = 170, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(qup_core_0_links), -+ .links = qup_core_0_links, -+}; -+ -+static const u16 link_slv_anoc_snoc[] = { -+ SM6115_SLAVE_ANOC_SNOC, -+}; -+ -+static struct qcom_icc_node crypto_c0 = { -+ .name = "crypto_c0", -+ .id = SM6115_MASTER_CRYPTO_CORE0, -+ .channels = 1, -+ .buswidth = 8, -+ .qos.qos_port = 43, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 2, -+ .mas_rpm_id = 23, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), -+ .links = link_slv_anoc_snoc, -+}; -+ -+static const u16 mas_snoc_cnoc_links[] = { -+ SM6115_SLAVE_AHB2PHY_USB, -+ SM6115_SLAVE_APSS_THROTTLE_CFG, -+ SM6115_SLAVE_BIMC_CFG, -+ SM6115_SLAVE_BOOT_ROM, -+ SM6115_SLAVE_CAMERA_CFG, -+ SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, -+ SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, -+ SM6115_SLAVE_CLK_CTL, -+ SM6115_SLAVE_CNOC_MSS, -+ SM6115_SLAVE_CRYPTO_0_CFG, -+ SM6115_SLAVE_DCC_CFG, -+ SM6115_SLAVE_DDR_PHY_CFG, -+ SM6115_SLAVE_DDR_SS_CFG, -+ SM6115_SLAVE_DISPLAY_CFG, -+ SM6115_SLAVE_DISPLAY_THROTTLE_CFG, -+ SM6115_SLAVE_GPU_CFG, -+ SM6115_SLAVE_GPU_THROTTLE_CFG, -+ SM6115_SLAVE_HWKM_CORE, -+ SM6115_SLAVE_IMEM_CFG, -+ SM6115_SLAVE_IPA_CFG, -+ SM6115_SLAVE_LPASS, -+ SM6115_SLAVE_MAPSS, -+ SM6115_SLAVE_MDSP_MPU_CFG, -+ SM6115_SLAVE_MESSAGE_RAM, -+ SM6115_SLAVE_PDM, -+ SM6115_SLAVE_PIMEM_CFG, -+ SM6115_SLAVE_PKA_CORE, -+ SM6115_SLAVE_PMIC_ARB, -+ SM6115_SLAVE_QDSS_CFG, -+ SM6115_SLAVE_QM_CFG, -+ SM6115_SLAVE_QM_MPU_CFG, -+ SM6115_SLAVE_QPIC, -+ SM6115_SLAVE_QUP_0, -+ SM6115_SLAVE_RBCPR_CX_CFG, -+ SM6115_SLAVE_RBCPR_MX_CFG, -+ SM6115_SLAVE_RPM, -+ SM6115_SLAVE_SDCC_1, -+ SM6115_SLAVE_SDCC_2, -+ SM6115_SLAVE_SECURITY, -+ SM6115_SLAVE_SERVICE_CNOC, -+ SM6115_SLAVE_SNOC_CFG, -+ SM6115_SLAVE_TCSR, -+ SM6115_SLAVE_TLMM, -+ SM6115_SLAVE_USB3, -+ SM6115_SLAVE_VENUS_CFG, -+ SM6115_SLAVE_VENUS_THROTTLE_CFG, -+ SM6115_SLAVE_VSENSE_CTRL_CFG, -+}; -+ -+static struct qcom_icc_node mas_snoc_cnoc = { -+ .name = "mas_snoc_cnoc", -+ .id = SM6115_MASTER_SNOC_CNOC, -+ .channels = 1, -+ .buswidth = 8, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), -+ .links = mas_snoc_cnoc_links, -+}; -+ -+static struct qcom_icc_node xm_dap = { -+ .name = "xm_dap", -+ .id = SM6115_MASTER_QDSS_DAP, -+ .channels = 1, -+ .buswidth = 8, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), -+ .links = mas_snoc_cnoc_links, -+}; -+ -+static const u16 link_slv_snoc_bimc_nrt[] = { -+ SM6115_SLAVE_SNOC_BIMC_NRT, -+}; -+ -+static struct qcom_icc_node qnm_camera_nrt = { -+ .name = "qnm_camera_nrt", -+ .id = SM6115_MASTER_CAMNOC_SF, -+ .channels = 1, -+ .buswidth = 32, -+ .qos.qos_port = 25, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 3, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), -+ .links = link_slv_snoc_bimc_nrt, -+}; -+ -+static struct qcom_icc_node qxm_venus0 = { -+ .name = "qxm_venus0", -+ .id = SM6115_MASTER_VIDEO_P0, -+ .channels = 1, -+ .buswidth = 16, -+ .qos.qos_port = 30, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 3, -+ .qos.urg_fwd_en = true, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), -+ .links = link_slv_snoc_bimc_nrt, -+}; -+ -+static struct qcom_icc_node qxm_venus_cpu = { -+ .name = "qxm_venus_cpu", -+ .id = SM6115_MASTER_VIDEO_PROC, -+ .channels = 1, -+ .buswidth = 8, -+ .qos.qos_port = 34, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), -+ .links = link_slv_snoc_bimc_nrt, -+}; -+ -+static const u16 link_slv_snoc_bimc_rt[] = { -+ SM6115_SLAVE_SNOC_BIMC_RT, -+}; -+ -+static struct qcom_icc_node qnm_camera_rt = { -+ .name = "qnm_camera_rt", -+ .id = SM6115_MASTER_CAMNOC_HF, -+ .channels = 1, -+ .buswidth = 32, -+ .qos.qos_port = 31, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 3, -+ .qos.urg_fwd_en = true, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_snoc_bimc_rt), -+ .links = link_slv_snoc_bimc_rt, -+}; -+ -+static struct qcom_icc_node qxm_mdp0 = { -+ .name = "qxm_mdp0", -+ .id = SM6115_MASTER_MDP_PORT0, -+ .channels = 1, -+ .buswidth = 16, -+ .qos.qos_port = 26, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 3, -+ .qos.urg_fwd_en = true, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_snoc_bimc_rt), -+ .links = link_slv_snoc_bimc_rt, -+}; -+ -+static const u16 slv_service_snoc_links[] = { -+ SM6115_SLAVE_SERVICE_SNOC, -+}; -+ -+static struct qcom_icc_node qhm_snoc_cfg = { -+ .name = "qhm_snoc_cfg", -+ .id = SM6115_MASTER_SNOC_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(slv_service_snoc_links), -+ .links = slv_service_snoc_links, -+}; -+ -+static const u16 mas_tic_links[] = { -+ SM6115_SLAVE_APPSS, -+ SM6115_SLAVE_OCIMEM, -+ SM6115_SLAVE_PIMEM, -+ SM6115_SLAVE_QDSS_STM, -+ SM6115_SLAVE_TCU, -+ SM6115_SLAVE_SNOC_BIMC, -+ SM6115_SLAVE_SNOC_CNOC, -+}; -+ -+static struct qcom_icc_node qhm_tic = { -+ .name = "qhm_tic", -+ .id = SM6115_MASTER_TIC, -+ .channels = 1, -+ .buswidth = 4, -+ .qos.qos_port = 29, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 2, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(mas_tic_links), -+ .links = mas_tic_links, -+}; -+ -+static struct qcom_icc_node mas_anoc_snoc = { -+ .name = "mas_anoc_snoc", -+ .id = SM6115_MASTER_ANOC_SNOC, -+ .channels = 1, -+ .buswidth = 16, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(mas_tic_links), -+ .links = mas_tic_links, -+}; -+ -+static const u16 mas_bimc_snoc_links[] = { -+ SM6115_SLAVE_APPSS, -+ SM6115_SLAVE_SNOC_CNOC, -+ SM6115_SLAVE_OCIMEM, -+ SM6115_SLAVE_PIMEM, -+ SM6115_SLAVE_QDSS_STM, -+ SM6115_SLAVE_TCU, -+}; -+ -+static struct qcom_icc_node mas_bimc_snoc = { -+ .name = "mas_bimc_snoc", -+ .id = SM6115_MASTER_BIMC_SNOC, -+ .channels = 1, -+ .buswidth = 8, -+ .mas_rpm_id = 21, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(mas_bimc_snoc_links), -+ .links = mas_bimc_snoc_links, -+}; -+ -+static const u16 mas_pimem_links[] = { -+ SM6115_SLAVE_OCIMEM, -+ SM6115_SLAVE_SNOC_BIMC, -+}; -+ -+static struct qcom_icc_node qxm_pimem = { -+ .name = "qxm_pimem", -+ .id = SM6115_MASTER_PIMEM, -+ .channels = 1, -+ .buswidth = 8, -+ .qos.qos_port = 41, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 2, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(mas_pimem_links), -+ .links = mas_pimem_links, -+}; -+ -+static struct qcom_icc_node qhm_qdss_bam = { -+ .name = "qhm_qdss_bam", -+ .id = SM6115_MASTER_QDSS_BAM, -+ .channels = 1, -+ .buswidth = 4, -+ .qos.qos_port = 23, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 2, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), -+ .links = link_slv_anoc_snoc, -+}; -+ -+static struct qcom_icc_node qhm_qpic = { -+ .name = "qhm_qpic", -+ .id = SM6115_MASTER_QPIC, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), -+ .links = link_slv_anoc_snoc, -+}; -+ -+static struct qcom_icc_node qhm_qup0 = { -+ .name = "qhm_qup0", -+ .id = SM6115_MASTER_QUP_0, -+ .channels = 1, -+ .buswidth = 4, -+ .qos.qos_port = 21, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 2, -+ .mas_rpm_id = 166, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), -+ .links = link_slv_anoc_snoc, -+}; -+ -+static struct qcom_icc_node qxm_ipa = { -+ .name = "qxm_ipa", -+ .id = SM6115_MASTER_IPA, -+ .channels = 1, -+ .buswidth = 8, -+ .qos.qos_port = 24, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 2, -+ .mas_rpm_id = 59, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), -+ .links = link_slv_anoc_snoc, -+}; -+ -+static struct qcom_icc_node xm_qdss_etr = { -+ .name = "xm_qdss_etr", -+ .id = SM6115_MASTER_QDSS_ETR, -+ .channels = 1, -+ .buswidth = 8, -+ .qos.qos_port = 33, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 2, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), -+ .links = link_slv_anoc_snoc, -+}; -+ -+static struct qcom_icc_node xm_sdc1 = { -+ .name = "xm_sdc1", -+ .id = SM6115_MASTER_SDCC_1, -+ .channels = 1, -+ .buswidth = 8, -+ .qos.qos_port = 38, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 2, -+ .mas_rpm_id = 33, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), -+ .links = link_slv_anoc_snoc, -+}; -+ -+static struct qcom_icc_node xm_sdc2 = { -+ .name = "xm_sdc2", -+ .id = SM6115_MASTER_SDCC_2, -+ .channels = 1, -+ .buswidth = 8, -+ .qos.qos_port = 44, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 2, -+ .mas_rpm_id = 35, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), -+ .links = link_slv_anoc_snoc, -+}; -+ -+static struct qcom_icc_node xm_usb3_0 = { -+ .name = "xm_usb3_0", -+ .id = SM6115_MASTER_USB3, -+ .channels = 1, -+ .buswidth = 8, -+ .qos.qos_port = 45, -+ .qos.qos_mode = NOC_QOS_MODE_FIXED, -+ .qos.areq_prio = 2, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(link_slv_anoc_snoc), -+ .links = link_slv_anoc_snoc, -+}; -+ -+static struct qcom_icc_node ebi = { -+ .name = "ebi", -+ .id = SM6115_SLAVE_EBI_CH0, -+ .channels = 1, -+ .buswidth = 8, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = 0, -+}; -+ -+static const u16 slv_bimc_snoc_links[] = { -+ SM6115_MASTER_BIMC_SNOC, -+}; -+ -+static struct qcom_icc_node slv_bimc_snoc = { -+ .name = "slv_bimc_snoc", -+ .id = SM6115_SLAVE_BIMC_SNOC, -+ .channels = 1, -+ .buswidth = 16, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = 2, -+ .num_links = ARRAY_SIZE(slv_bimc_snoc_links), -+ .links = slv_bimc_snoc_links, -+}; -+ -+static struct qcom_icc_node qup0_core_slave = { -+ .name = "qup0_core_slave", -+ .id = SM6115_SLAVE_QUP_CORE_0, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_ahb2phy_usb = { -+ .name = "qhs_ahb2phy_usb", -+ .id = SM6115_SLAVE_AHB2PHY_USB, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_apss_throttle_cfg = { -+ .name = "qhs_apss_throttle_cfg", -+ .id = SM6115_SLAVE_APSS_THROTTLE_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_bimc_cfg = { -+ .name = "qhs_bimc_cfg", -+ .id = SM6115_SLAVE_BIMC_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_boot_rom = { -+ .name = "qhs_boot_rom", -+ .id = SM6115_SLAVE_BOOT_ROM, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { -+ .name = "qhs_camera_nrt_throttle_cfg", -+ .id = SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { -+ .name = "qhs_camera_rt_throttle_cfg", -+ .id = SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_camera_ss_cfg = { -+ .name = "qhs_camera_ss_cfg", -+ .id = SM6115_SLAVE_CAMERA_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_clk_ctl = { -+ .name = "qhs_clk_ctl", -+ .id = SM6115_SLAVE_CLK_CTL, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_cpr_cx = { -+ .name = "qhs_cpr_cx", -+ .id = SM6115_SLAVE_RBCPR_CX_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_cpr_mx = { -+ .name = "qhs_cpr_mx", -+ .id = SM6115_SLAVE_RBCPR_MX_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_crypto0_cfg = { -+ .name = "qhs_crypto0_cfg", -+ .id = SM6115_SLAVE_CRYPTO_0_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_dcc_cfg = { -+ .name = "qhs_dcc_cfg", -+ .id = SM6115_SLAVE_DCC_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_ddr_phy_cfg = { -+ .name = "qhs_ddr_phy_cfg", -+ .id = SM6115_SLAVE_DDR_PHY_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_ddr_ss_cfg = { -+ .name = "qhs_ddr_ss_cfg", -+ .id = SM6115_SLAVE_DDR_SS_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_disp_ss_cfg = { -+ .name = "qhs_disp_ss_cfg", -+ .id = SM6115_SLAVE_DISPLAY_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_display_throttle_cfg = { -+ .name = "qhs_display_throttle_cfg", -+ .id = SM6115_SLAVE_DISPLAY_THROTTLE_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_gpu_cfg = { -+ .name = "qhs_gpu_cfg", -+ .id = SM6115_SLAVE_GPU_CFG, -+ .channels = 1, -+ .buswidth = 8, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_gpu_throttle_cfg = { -+ .name = "qhs_gpu_throttle_cfg", -+ .id = SM6115_SLAVE_GPU_THROTTLE_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_hwkm = { -+ .name = "qhs_hwkm", -+ .id = SM6115_SLAVE_HWKM_CORE, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_imem_cfg = { -+ .name = "qhs_imem_cfg", -+ .id = SM6115_SLAVE_IMEM_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_ipa_cfg = { -+ .name = "qhs_ipa_cfg", -+ .id = SM6115_SLAVE_IPA_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_lpass = { -+ .name = "qhs_lpass", -+ .id = SM6115_SLAVE_LPASS, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_mapss = { -+ .name = "qhs_mapss", -+ .id = SM6115_SLAVE_MAPSS, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_mdsp_mpu_cfg = { -+ .name = "qhs_mdsp_mpu_cfg", -+ .id = SM6115_SLAVE_MDSP_MPU_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_mesg_ram = { -+ .name = "qhs_mesg_ram", -+ .id = SM6115_SLAVE_MESSAGE_RAM, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_mss = { -+ .name = "qhs_mss", -+ .id = SM6115_SLAVE_CNOC_MSS, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_pdm = { -+ .name = "qhs_pdm", -+ .id = SM6115_SLAVE_PDM, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_pimem_cfg = { -+ .name = "qhs_pimem_cfg", -+ .id = SM6115_SLAVE_PIMEM_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_pka_wrapper = { -+ .name = "qhs_pka_wrapper", -+ .id = SM6115_SLAVE_PKA_CORE, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_pmic_arb = { -+ .name = "qhs_pmic_arb", -+ .id = SM6115_SLAVE_PMIC_ARB, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_qdss_cfg = { -+ .name = "qhs_qdss_cfg", -+ .id = SM6115_SLAVE_QDSS_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_qm_cfg = { -+ .name = "qhs_qm_cfg", -+ .id = SM6115_SLAVE_QM_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_qm_mpu_cfg = { -+ .name = "qhs_qm_mpu_cfg", -+ .id = SM6115_SLAVE_QM_MPU_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_qpic = { -+ .name = "qhs_qpic", -+ .id = SM6115_SLAVE_QPIC, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_qup0 = { -+ .name = "qhs_qup0", -+ .id = SM6115_SLAVE_QUP_0, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_rpm = { -+ .name = "qhs_rpm", -+ .id = SM6115_SLAVE_RPM, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_sdc1 = { -+ .name = "qhs_sdc1", -+ .id = SM6115_SLAVE_SDCC_1, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_sdc2 = { -+ .name = "qhs_sdc2", -+ .id = SM6115_SLAVE_SDCC_2, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_security = { -+ .name = "qhs_security", -+ .id = SM6115_SLAVE_SECURITY, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static const u16 slv_snoc_cfg_links[] = { -+ SM6115_MASTER_SNOC_CFG, -+}; -+ -+static struct qcom_icc_node qhs_snoc_cfg = { -+ .name = "qhs_snoc_cfg", -+ .id = SM6115_SLAVE_SNOC_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(slv_snoc_cfg_links), -+ .links = slv_snoc_cfg_links, -+}; -+ -+static struct qcom_icc_node qhs_tcsr = { -+ .name = "qhs_tcsr", -+ .id = SM6115_SLAVE_TCSR, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_tlmm = { -+ .name = "qhs_tlmm", -+ .id = SM6115_SLAVE_TLMM, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_usb3 = { -+ .name = "qhs_usb3", -+ .id = SM6115_SLAVE_USB3, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_venus_cfg = { -+ .name = "qhs_venus_cfg", -+ .id = SM6115_SLAVE_VENUS_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_venus_throttle_cfg = { -+ .name = "qhs_venus_throttle_cfg", -+ .id = SM6115_SLAVE_VENUS_THROTTLE_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node qhs_vsense_ctrl_cfg = { -+ .name = "qhs_vsense_ctrl_cfg", -+ .id = SM6115_SLAVE_VSENSE_CTRL_CFG, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node srvc_cnoc = { -+ .name = "srvc_cnoc", -+ .id = SM6115_SLAVE_SERVICE_CNOC, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static const u16 slv_snoc_bimc_nrt_links[] = { -+ SM6115_MASTER_SNOC_BIMC_NRT, -+}; -+ -+static struct qcom_icc_node slv_snoc_bimc_nrt = { -+ .name = "slv_snoc_bimc_nrt", -+ .id = SM6115_SLAVE_SNOC_BIMC_NRT, -+ .channels = 1, -+ .buswidth = 16, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links), -+ .links = slv_snoc_bimc_nrt_links, -+}; -+ -+static const u16 slv_snoc_bimc_rt_links[] = { -+ SM6115_MASTER_SNOC_BIMC_RT, -+}; -+ -+static struct qcom_icc_node slv_snoc_bimc_rt = { -+ .name = "slv_snoc_bimc_rt", -+ .id = SM6115_SLAVE_SNOC_BIMC_RT, -+ .channels = 1, -+ .buswidth = 16, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links), -+ .links = slv_snoc_bimc_rt_links, -+}; -+ -+static struct qcom_icc_node qhs_apss = { -+ .name = "qhs_apss", -+ .id = SM6115_SLAVE_APPSS, -+ .channels = 1, -+ .buswidth = 8, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static const u16 slv_snoc_cnoc_links[] = { -+ SM6115_MASTER_SNOC_CNOC -+}; -+ -+static struct qcom_icc_node slv_snoc_cnoc = { -+ .name = "slv_snoc_cnoc", -+ .id = SM6115_SLAVE_SNOC_CNOC, -+ .channels = 1, -+ .buswidth = 8, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = 25, -+ .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), -+ .links = slv_snoc_cnoc_links, -+}; -+ -+static struct qcom_icc_node qxs_imem = { -+ .name = "qxs_imem", -+ .id = SM6115_SLAVE_OCIMEM, -+ .channels = 1, -+ .buswidth = 8, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = 26, -+}; -+ -+static struct qcom_icc_node qxs_pimem = { -+ .name = "qxs_pimem", -+ .id = SM6115_SLAVE_PIMEM, -+ .channels = 1, -+ .buswidth = 8, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static const u16 slv_snoc_bimc_links[] = { -+ SM6115_MASTER_SNOC_BIMC, -+}; -+ -+static struct qcom_icc_node slv_snoc_bimc = { -+ .name = "slv_snoc_bimc", -+ .id = SM6115_SLAVE_SNOC_BIMC, -+ .channels = 1, -+ .buswidth = 16, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = 24, -+ .num_links = ARRAY_SIZE(slv_snoc_bimc_links), -+ .links = slv_snoc_bimc_links, -+}; -+ -+static struct qcom_icc_node srvc_snoc = { -+ .name = "srvc_snoc", -+ .id = SM6115_SLAVE_SERVICE_SNOC, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static struct qcom_icc_node xs_qdss_stm = { -+ .name = "xs_qdss_stm", -+ .id = SM6115_SLAVE_QDSS_STM, -+ .channels = 1, -+ .buswidth = 4, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = 30, -+}; -+ -+static struct qcom_icc_node xs_sys_tcu_cfg = { -+ .name = "xs_sys_tcu_cfg", -+ .id = SM6115_SLAVE_TCU, -+ .channels = 1, -+ .buswidth = 8, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+}; -+ -+static const u16 slv_anoc_snoc_links[] = { -+ SM6115_MASTER_ANOC_SNOC, -+}; -+ -+static struct qcom_icc_node slv_anoc_snoc = { -+ .name = "slv_anoc_snoc", -+ .id = SM6115_SLAVE_ANOC_SNOC, -+ .channels = 1, -+ .buswidth = 16, -+ .mas_rpm_id = -1, -+ .slv_rpm_id = -1, -+ .num_links = ARRAY_SIZE(slv_anoc_snoc_links), -+ .links = slv_anoc_snoc_links, -+}; -+ -+static struct qcom_icc_node *bimc_nodes[] = { -+ [MASTER_AMPSS_M0] = &apps_proc, -+ [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, -+ [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, -+ [SNOC_BIMC_MAS] = &mas_snoc_bimc, -+ [MASTER_GRAPHICS_3D] = &qnm_gpu, -+ [MASTER_TCU_0] = &tcu_0, -+ [SLAVE_EBI_CH0] = &ebi, -+ [BIMC_SNOC_SLV] = &slv_bimc_snoc, -+}; -+ -+static const struct regmap_config bimc_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .max_register = 0x80000, -+ .fast_io = true, -+}; -+ -+static const struct qcom_icc_desc sm6115_bimc = { -+ .type = QCOM_ICC_BIMC, -+ .nodes = bimc_nodes, -+ .num_nodes = ARRAY_SIZE(bimc_nodes), -+ .regmap_cfg = &bimc_regmap_config, -+ .bus_clk_desc = &bimc_clk, -+ .keep_alive = true, -+ .qos_offset = 0x8000, -+}; -+ -+static struct qcom_icc_node *config_noc_nodes[] = { -+ [SNOC_CNOC_MAS] = &mas_snoc_cnoc, -+ [MASTER_QDSS_DAP] = &xm_dap, -+ [SLAVE_AHB2PHY_USB] = &qhs_ahb2phy_usb, -+ [SLAVE_APSS_THROTTLE_CFG] = &qhs_apss_throttle_cfg, -+ [SLAVE_BIMC_CFG] = &qhs_bimc_cfg, -+ [SLAVE_BOOT_ROM] = &qhs_boot_rom, -+ [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, -+ [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, -+ [SLAVE_CAMERA_CFG] = &qhs_camera_ss_cfg, -+ [SLAVE_CLK_CTL] = &qhs_clk_ctl, -+ [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, -+ [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, -+ [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, -+ [SLAVE_DCC_CFG] = &qhs_dcc_cfg, -+ [SLAVE_DDR_PHY_CFG] = &qhs_ddr_phy_cfg, -+ [SLAVE_DDR_SS_CFG] = &qhs_ddr_ss_cfg, -+ [SLAVE_DISPLAY_CFG] = &qhs_disp_ss_cfg, -+ [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, -+ [SLAVE_GPU_CFG] = &qhs_gpu_cfg, -+ [SLAVE_GPU_THROTTLE_CFG] = &qhs_gpu_throttle_cfg, -+ [SLAVE_HWKM_CORE] = &qhs_hwkm, -+ [SLAVE_IMEM_CFG] = &qhs_imem_cfg, -+ [SLAVE_IPA_CFG] = &qhs_ipa_cfg, -+ [SLAVE_LPASS] = &qhs_lpass, -+ [SLAVE_MAPSS] = &qhs_mapss, -+ [SLAVE_MDSP_MPU_CFG] = &qhs_mdsp_mpu_cfg, -+ [SLAVE_MESSAGE_RAM] = &qhs_mesg_ram, -+ [SLAVE_CNOC_MSS] = &qhs_mss, -+ [SLAVE_PDM] = &qhs_pdm, -+ [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, -+ [SLAVE_PKA_CORE] = &qhs_pka_wrapper, -+ [SLAVE_PMIC_ARB] = &qhs_pmic_arb, -+ [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, -+ [SLAVE_QM_CFG] = &qhs_qm_cfg, -+ [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, -+ [SLAVE_QPIC] = &qhs_qpic, -+ [SLAVE_QUP_0] = &qhs_qup0, -+ [SLAVE_RPM] = &qhs_rpm, -+ [SLAVE_SDCC_1] = &qhs_sdc1, -+ [SLAVE_SDCC_2] = &qhs_sdc2, -+ [SLAVE_SECURITY] = &qhs_security, -+ [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, -+ [SLAVE_TCSR] = &qhs_tcsr, -+ [SLAVE_TLMM] = &qhs_tlmm, -+ [SLAVE_USB3] = &qhs_usb3, -+ [SLAVE_VENUS_CFG] = &qhs_venus_cfg, -+ [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, -+ [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, -+ [SLAVE_SERVICE_CNOC] = &srvc_cnoc, -+}; -+ -+static const struct regmap_config cnoc_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .max_register = 0x6200, -+ .fast_io = true, -+}; -+ -+static const struct qcom_icc_desc sm6115_config_noc = { -+ .type = QCOM_ICC_QNOC, -+ .nodes = config_noc_nodes, -+ .num_nodes = ARRAY_SIZE(config_noc_nodes), -+ .regmap_cfg = &cnoc_regmap_config, -+ .intf_clocks = cnoc_intf_clocks, -+ .num_intf_clocks = ARRAY_SIZE(cnoc_intf_clocks), -+ .bus_clk_desc = &bus_1_clk, -+ .keep_alive = true, -+}; -+ -+static struct qcom_icc_node *sys_noc_nodes[] = { -+ [MASTER_CRYPTO_CORE0] = &crypto_c0, -+ [MASTER_SNOC_CFG] = &qhm_snoc_cfg, -+ [MASTER_TIC] = &qhm_tic, -+ [MASTER_ANOC_SNOC] = &mas_anoc_snoc, -+ [BIMC_SNOC_MAS] = &mas_bimc_snoc, -+ [MASTER_PIMEM] = &qxm_pimem, -+ [MASTER_QDSS_BAM] = &qhm_qdss_bam, -+ [MASTER_QPIC] = &qhm_qpic, -+ [MASTER_QUP_0] = &qhm_qup0, -+ [MASTER_IPA] = &qxm_ipa, -+ [MASTER_QDSS_ETR] = &xm_qdss_etr, -+ [MASTER_SDCC_1] = &xm_sdc1, -+ [MASTER_SDCC_2] = &xm_sdc2, -+ [MASTER_USB3] = &xm_usb3_0, -+ [SLAVE_APPSS] = &qhs_apss, -+ [SNOC_CNOC_SLV] = &slv_snoc_cnoc, -+ [SLAVE_OCIMEM] = &qxs_imem, -+ [SLAVE_PIMEM] = &qxs_pimem, -+ [SNOC_BIMC_SLV] = &slv_snoc_bimc, -+ [SLAVE_SERVICE_SNOC] = &srvc_snoc, -+ [SLAVE_QDSS_STM] = &xs_qdss_stm, -+ [SLAVE_TCU] = &xs_sys_tcu_cfg, -+ [SLAVE_ANOC_SNOC] = &slv_anoc_snoc, -+}; -+ -+static const struct regmap_config sys_noc_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .max_register = 0x5f080, -+ .fast_io = true, -+}; -+ -+static const struct qcom_icc_desc sm6115_sys_noc = { -+ .type = QCOM_ICC_QNOC, -+ .nodes = sys_noc_nodes, -+ .num_nodes = ARRAY_SIZE(sys_noc_nodes), -+ .regmap_cfg = &sys_noc_regmap_config, -+ .intf_clocks = snoc_intf_clocks, -+ .num_intf_clocks = ARRAY_SIZE(snoc_intf_clocks), -+ .bus_clk_desc = &bus_2_clk, -+ .keep_alive = true, -+}; -+ -+static struct qcom_icc_node *clk_virt_nodes[] = { -+ [MASTER_QUP_CORE_0] = &qup0_core_master, -+ [SLAVE_QUP_CORE_0] = &qup0_core_slave, -+}; -+ -+static const struct qcom_icc_desc sm6115_clk_virt = { -+ .type = QCOM_ICC_QNOC, -+ .nodes = clk_virt_nodes, -+ .num_nodes = ARRAY_SIZE(clk_virt_nodes), -+ .regmap_cfg = &sys_noc_regmap_config, -+ .bus_clk_desc = &qup_clk, -+ .keep_alive = true, -+}; -+ -+static struct qcom_icc_node *mmnrt_virt_nodes[] = { -+ [MASTER_CAMNOC_SF] = &qnm_camera_nrt, -+ [MASTER_VIDEO_P0] = &qxm_venus0, -+ [MASTER_VIDEO_PROC] = &qxm_venus_cpu, -+ [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, -+}; -+ -+static const struct qcom_icc_desc sm6115_mmnrt_virt = { -+ .type = QCOM_ICC_QNOC, -+ .nodes = mmnrt_virt_nodes, -+ .num_nodes = ARRAY_SIZE(mmnrt_virt_nodes), -+ .regmap_cfg = &sys_noc_regmap_config, -+ .bus_clk_desc = &mmaxi_0_clk, -+ .keep_alive = true, -+}; -+ -+static struct qcom_icc_node *mmrt_virt_nodes[] = { -+ [MASTER_CAMNOC_HF] = &qnm_camera_rt, -+ [MASTER_MDP_PORT0] = &qxm_mdp0, -+ [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, -+}; -+ -+static const struct qcom_icc_desc sm6115_mmrt_virt = { -+ .type = QCOM_ICC_QNOC, -+ .nodes = mmrt_virt_nodes, -+ .num_nodes = ARRAY_SIZE(mmrt_virt_nodes), -+ .regmap_cfg = &sys_noc_regmap_config, -+ .bus_clk_desc = &mmaxi_1_clk, -+ .keep_alive = true, -+}; -+ -+static const struct of_device_id qnoc_of_match[] = { -+ { .compatible = "qcom,sm6115-bimc", .data = &sm6115_bimc }, -+ { .compatible = "qcom,sm6115-clk-virt", .data = &sm6115_clk_virt }, -+ { .compatible = "qcom,sm6115-cnoc", .data = &sm6115_config_noc }, -+ { .compatible = "qcom,sm6115-mmrt-virt", .data = &sm6115_mmrt_virt }, -+ { .compatible = "qcom,sm6115-mmnrt-virt", .data = &sm6115_mmnrt_virt }, -+ { .compatible = "qcom,sm6115-snoc", .data = &sm6115_sys_noc }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, qnoc_of_match); -+ -+static struct platform_driver qnoc_driver = { -+ .probe = qnoc_probe, -+ .remove = qnoc_remove, -+ .driver = { -+ .name = "qnoc-sm6115", -+ .of_match_table = qnoc_of_match, -+ .sync_state = icc_sync_state, -+ }, -+}; -+ -+static int __init qnoc_driver_init(void) -+{ -+ return platform_driver_register(&qnoc_driver); -+} -+core_initcall(qnoc_driver_init); -+ -+static void __exit qnoc_driver_exit(void) -+{ -+ platform_driver_unregister(&qnoc_driver); -+} -+module_exit(qnoc_driver_exit); -+ -+MODULE_DESCRIPTION("SM6115 NoC driver"); -+MODULE_LICENSE("GPL"); -\ No newline at end of file -diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -index d326fa230b9..c74b2eee686 100644 ---- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -@@ -246,6 +246,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { - { .compatible = "qcom,adreno-gmu" }, - { .compatible = "qcom,mdp4" }, - { .compatible = "qcom,mdss" }, -+ { .compatible = "qcom,qcm2290-mdss" }, - { .compatible = "qcom,sc7180-mdss" }, - { .compatible = "qcom,sc7180-mss-pil" }, - { .compatible = "qcom,sc7280-mdss" }, -@@ -255,6 +256,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { - { .compatible = "qcom,sdm670-mdss" }, - { .compatible = "qcom,sdm845-mdss" }, - { .compatible = "qcom,sdm845-mss-pil" }, -+ { .compatible = "qcom,sm6115-mdss" }, - { .compatible = "qcom,sm6350-mdss" }, - { .compatible = "qcom,sm6375-mdss" }, - { .compatible = "qcom,sm8150-mdss" }, -diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig -index 59ee0ca2c97..34cc13370d2 100644 ---- a/drivers/media/i2c/Kconfig -+++ b/drivers/media/i2c/Kconfig -@@ -201,6 +201,20 @@ config VIDEO_IMX415 - To compile this driver as a module, choose M here: the - module will be called imx415. - -+config VIDEO_IMX519 -+ tristate "Sony IMX519 sensor support" -+ depends on I2C && VIDEO_DEV -+ select MEDIA_CONTROLLER -+ select VIDEO_V4L2_SUBDEV_API -+ select V4L2_CCI_I2C -+ select V4L2_FWNODE -+ help -+ This is a Video4Linux2 sensor driver for the Sony -+ IMX519 camera. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called imx519. -+ - config VIDEO_MAX9271_LIB - tristate - -diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile -index f5010f80a21..b8c543f0a03 100644 ---- a/drivers/media/i2c/Makefile -+++ b/drivers/media/i2c/Makefile -@@ -53,6 +53,7 @@ obj-$(CONFIG_VIDEO_IMX335) += imx335.o - obj-$(CONFIG_VIDEO_IMX355) += imx355.o - obj-$(CONFIG_VIDEO_IMX412) += imx412.o - obj-$(CONFIG_VIDEO_IMX415) += imx415.o -+obj-$(CONFIG_VIDEO_IMX519) += imx519.o - obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o - obj-$(CONFIG_VIDEO_ISL7998X) += isl7998x.o - obj-$(CONFIG_VIDEO_KS0127) += ks0127.o -diff --git a/drivers/media/i2c/imx519.c b/drivers/media/i2c/imx519.c -new file mode 100644 -index 00000000000..5d799209817 ---- /dev/null -+++ b/drivers/media/i2c/imx519.c -@@ -0,0 +1,1864 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * A V4L2 driver for Sony IMX519 cameras. -+ * Copyright (C) 2022 Arducam Technology co., Ltd. -+ * -+ * Based on Sony IMX477 camera driver -+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Chip ID */ -+#define IMX519_REG_CHIP_ID CCI_REG16(0x0016) -+#define IMX519_CHIP_ID 0x0519 -+ -+#define IMX519_REG_MODE_SELECT CCI_REG8(0x0100) -+#define IMX519_MODE_STANDBY 0x00 -+#define IMX519_MODE_STREAMING 0x01 -+ -+#define IMX519_REG_ORIENTATION CCI_REG8(0x101) -+ -+#define IMX519_XCLK_FREQ 24000000 -+ -+#define IMX519_DEFAULT_LINK_FREQ 493500000 -+ -+/* Pixel rate is fixed at 686MHz for all the modes */ -+#define IMX519_PIXEL_RATE 426666667 -+ -+/* V_TIMING internal */ -+#define IMX519_REG_FRAME_LENGTH CCI_REG16(0x0340) -+#define IMX519_FRAME_LENGTH_MAX 0xffdc -+ -+/* Long exposure multiplier */ -+#define IMX519_LONG_EXP_SHIFT_MAX 7 -+#define IMX519_LONG_EXP_SHIFT_REG CCI_REG8(0x3100) -+ -+/* Exposure control */ -+#define IMX519_REG_EXPOSURE CCI_REG16(0x0202) -+#define IMX519_EXPOSURE_OFFSET 32 -+#define IMX519_EXPOSURE_MIN 20 -+#define IMX519_EXPOSURE_STEP 1 -+#define IMX519_EXPOSURE_DEFAULT 0x3e8 -+#define IMX519_EXPOSURE_MAX (IMX519_FRAME_LENGTH_MAX - \ -+ IMX519_EXPOSURE_OFFSET) -+ -+/* Analog gain control */ -+#define IMX519_REG_ANALOG_GAIN CCI_REG16(0x0204) -+#define IMX519_ANA_GAIN_MIN 0 -+#define IMX519_ANA_GAIN_MAX 960 -+#define IMX519_ANA_GAIN_STEP 1 -+#define IMX519_ANA_GAIN_DEFAULT 0x0 -+ -+/* Digital gain control */ -+#define IMX519_REG_DIGITAL_GAIN CCI_REG16(0x020e) -+#define IMX519_DGTL_GAIN_MIN 0x0100 -+#define IMX519_DGTL_GAIN_MAX 0xffff -+#define IMX519_DGTL_GAIN_DEFAULT 0x0100 -+#define IMX519_DGTL_GAIN_STEP 1 -+ -+/* Test Pattern Control */ -+#define IMX519_REG_TEST_PATTERN CCI_REG16(0x0600) -+#define IMX519_TEST_PATTERN_DISABLE 0 -+#define IMX519_TEST_PATTERN_SOLID_COLOR 1 -+#define IMX519_TEST_PATTERN_COLOR_BARS 2 -+#define IMX519_TEST_PATTERN_GREY_COLOR 3 -+#define IMX519_TEST_PATTERN_PN9 4 -+ -+/* Test pattern colour components */ -+#define IMX519_REG_TEST_PATTERN_R CCI_REG16(0x0602) -+#define IMX519_REG_TEST_PATTERN_GR CCI_REG16(0x0604) -+#define IMX519_REG_TEST_PATTERN_B CCI_REG16(0x0606) -+#define IMX519_REG_TEST_PATTERN_GB CCI_REG16(0x0608) -+#define IMX519_TEST_PATTERN_COLOUR_MIN 0 -+#define IMX519_TEST_PATTERN_COLOUR_MAX 0x0fff -+#define IMX519_TEST_PATTERN_COLOUR_STEP 1 -+#define IMX519_TEST_PATTERN_R_DEFAULT IMX519_TEST_PATTERN_COLOUR_MAX -+#define IMX519_TEST_PATTERN_GR_DEFAULT 0 -+#define IMX519_TEST_PATTERN_B_DEFAULT 0 -+#define IMX519_TEST_PATTERN_GB_DEFAULT 0 -+ -+/* IMX519 native and active pixel array size. */ -+#define IMX519_NATIVE_WIDTH 4672U -+#define IMX519_NATIVE_HEIGHT 3648U -+#define IMX519_PIXEL_ARRAY_LEFT 8U -+#define IMX519_PIXEL_ARRAY_TOP 48U -+#define IMX519_PIXEL_ARRAY_WIDTH 4656U -+#define IMX519_PIXEL_ARRAY_HEIGHT 3496U -+ -+struct imx519_reg_list { -+ unsigned int num_of_regs; -+ const struct cci_reg_sequence *regs; -+}; -+ -+/* Mode : resolution and related config&values */ -+struct imx519_mode { -+ /* Frame width */ -+ unsigned int width; -+ -+ /* Frame height */ -+ unsigned int height; -+ -+ /* H-timing in pixels */ -+ unsigned int line_length_pix; -+ -+ /* Analog crop rectangle. */ -+ struct v4l2_rect crop; -+ -+ /* Highest possible framerate. */ -+ struct v4l2_fract timeperframe_min; -+ -+ /* Default framerate. */ -+ struct v4l2_fract timeperframe_default; -+ -+ /* Default register values */ -+ struct imx519_reg_list reg_list; -+}; -+ -+static const struct cci_reg_sequence mode_common_regs[] = { -+ { CCI_REG8(0x0136), 0x18 }, -+ { CCI_REG8(0x0137), 0x00 }, -+ { CCI_REG8(0x3c7e), 0x01 }, -+ { CCI_REG8(0x3c7f), 0x07 }, -+ { CCI_REG8(0x3020), 0x00 }, -+ { CCI_REG8(0x3e35), 0x01 }, -+ { CCI_REG8(0x3f7f), 0x01 }, -+ { CCI_REG8(0x5609), 0x57 }, -+ { CCI_REG8(0x5613), 0x51 }, -+ { CCI_REG8(0x561f), 0x5e }, -+ { CCI_REG8(0x5623), 0xd2 }, -+ { CCI_REG8(0x5637), 0x11 }, -+ { CCI_REG8(0x5657), 0x11 }, -+ { CCI_REG8(0x5659), 0x12 }, -+ { CCI_REG8(0x5733), 0x60 }, -+ { CCI_REG8(0x5905), 0x57 }, -+ { CCI_REG8(0x590f), 0x51 }, -+ { CCI_REG8(0x591b), 0x5e }, -+ { CCI_REG8(0x591f), 0xd2 }, -+ { CCI_REG8(0x5933), 0x11 }, -+ { CCI_REG8(0x5953), 0x11 }, -+ { CCI_REG8(0x5955), 0x12 }, -+ { CCI_REG8(0x5a2f), 0x60 }, -+ { CCI_REG8(0x5a85), 0x57 }, -+ { CCI_REG8(0x5a8f), 0x51 }, -+ { CCI_REG8(0x5a9b), 0x5e }, -+ { CCI_REG8(0x5a9f), 0xd2 }, -+ { CCI_REG8(0x5ab3), 0x11 }, -+ { CCI_REG8(0x5ad3), 0x11 }, -+ { CCI_REG8(0x5ad5), 0x12 }, -+ { CCI_REG8(0x5baf), 0x60 }, -+ { CCI_REG8(0x5c15), 0x2a }, -+ { CCI_REG8(0x5c17), 0x80 }, -+ { CCI_REG8(0x5c19), 0x31 }, -+ { CCI_REG8(0x5c1b), 0x87 }, -+ { CCI_REG8(0x5c25), 0x25 }, -+ { CCI_REG8(0x5c27), 0x7b }, -+ { CCI_REG8(0x5c29), 0x2a }, -+ { CCI_REG8(0x5c2b), 0x80 }, -+ { CCI_REG8(0x5c2d), 0x31 }, -+ { CCI_REG8(0x5c2f), 0x87 }, -+ { CCI_REG8(0x5c35), 0x2b }, -+ { CCI_REG8(0x5c37), 0x81 }, -+ { CCI_REG8(0x5c39), 0x31 }, -+ { CCI_REG8(0x5c3b), 0x87 }, -+ { CCI_REG8(0x5c45), 0x25 }, -+ { CCI_REG8(0x5c47), 0x7b }, -+ { CCI_REG8(0x5c49), 0x2a }, -+ { CCI_REG8(0x5c4b), 0x80 }, -+ { CCI_REG8(0x5c4d), 0x31 }, -+ { CCI_REG8(0x5c4f), 0x87 }, -+ { CCI_REG8(0x5c55), 0x2d }, -+ { CCI_REG8(0x5c57), 0x83 }, -+ { CCI_REG8(0x5c59), 0x32 }, -+ { CCI_REG8(0x5c5b), 0x88 }, -+ { CCI_REG8(0x5c65), 0x29 }, -+ { CCI_REG8(0x5c67), 0x7f }, -+ { CCI_REG8(0x5c69), 0x2e }, -+ { CCI_REG8(0x5c6b), 0x84 }, -+ { CCI_REG8(0x5c6d), 0x32 }, -+ { CCI_REG8(0x5c6f), 0x88 }, -+ { CCI_REG8(0x5e69), 0x04 }, -+ { CCI_REG8(0x5e9d), 0x00 }, -+ { CCI_REG8(0x5f18), 0x10 }, -+ { CCI_REG8(0x5f1a), 0x0e }, -+ { CCI_REG8(0x5f20), 0x12 }, -+ { CCI_REG8(0x5f22), 0x10 }, -+ { CCI_REG8(0x5f24), 0x0e }, -+ { CCI_REG8(0x5f28), 0x10 }, -+ { CCI_REG8(0x5f2a), 0x0e }, -+ { CCI_REG8(0x5f30), 0x12 }, -+ { CCI_REG8(0x5f32), 0x10 }, -+ { CCI_REG8(0x5f34), 0x0e }, -+ { CCI_REG8(0x5f38), 0x0f }, -+ { CCI_REG8(0x5f39), 0x0d }, -+ { CCI_REG8(0x5f3c), 0x11 }, -+ { CCI_REG8(0x5f3d), 0x0f }, -+ { CCI_REG8(0x5f3e), 0x0d }, -+ { CCI_REG8(0x5f61), 0x07 }, -+ { CCI_REG8(0x5f64), 0x05 }, -+ { CCI_REG8(0x5f67), 0x03 }, -+ { CCI_REG8(0x5f6a), 0x03 }, -+ { CCI_REG8(0x5f6d), 0x07 }, -+ { CCI_REG8(0x5f70), 0x07 }, -+ { CCI_REG8(0x5f73), 0x05 }, -+ { CCI_REG8(0x5f76), 0x02 }, -+ { CCI_REG8(0x5f79), 0x07 }, -+ { CCI_REG8(0x5f7c), 0x07 }, -+ { CCI_REG8(0x5f7f), 0x07 }, -+ { CCI_REG8(0x5f82), 0x07 }, -+ { CCI_REG8(0x5f85), 0x03 }, -+ { CCI_REG8(0x5f88), 0x02 }, -+ { CCI_REG8(0x5f8b), 0x01 }, -+ { CCI_REG8(0x5f8e), 0x01 }, -+ { CCI_REG8(0x5f91), 0x04 }, -+ { CCI_REG8(0x5f94), 0x05 }, -+ { CCI_REG8(0x5f97), 0x02 }, -+ { CCI_REG8(0x5f9d), 0x07 }, -+ { CCI_REG8(0x5fa0), 0x07 }, -+ { CCI_REG8(0x5fa3), 0x07 }, -+ { CCI_REG8(0x5fa6), 0x07 }, -+ { CCI_REG8(0x5fa9), 0x03 }, -+ { CCI_REG8(0x5fac), 0x01 }, -+ { CCI_REG8(0x5faf), 0x01 }, -+ { CCI_REG8(0x5fb5), 0x03 }, -+ { CCI_REG8(0x5fb8), 0x02 }, -+ { CCI_REG8(0x5fbb), 0x01 }, -+ { CCI_REG8(0x5fc1), 0x07 }, -+ { CCI_REG8(0x5fc4), 0x07 }, -+ { CCI_REG8(0x5fc7), 0x07 }, -+ { CCI_REG8(0x5fd1), 0x00 }, -+ { CCI_REG8(0x6302), 0x79 }, -+ { CCI_REG8(0x6305), 0x78 }, -+ { CCI_REG8(0x6306), 0xa5 }, -+ { CCI_REG8(0x6308), 0x03 }, -+ { CCI_REG8(0x6309), 0x20 }, -+ { CCI_REG8(0x630b), 0x0a }, -+ { CCI_REG8(0x630d), 0x48 }, -+ { CCI_REG8(0x630f), 0x06 }, -+ { CCI_REG8(0x6311), 0xa4 }, -+ { CCI_REG8(0x6313), 0x03 }, -+ { CCI_REG8(0x6314), 0x20 }, -+ { CCI_REG8(0x6316), 0x0a }, -+ { CCI_REG8(0x6317), 0x31 }, -+ { CCI_REG8(0x6318), 0x4a }, -+ { CCI_REG8(0x631a), 0x06 }, -+ { CCI_REG8(0x631b), 0x40 }, -+ { CCI_REG8(0x631c), 0xa4 }, -+ { CCI_REG8(0x631e), 0x03 }, -+ { CCI_REG8(0x631f), 0x20 }, -+ { CCI_REG8(0x6321), 0x0a }, -+ { CCI_REG8(0x6323), 0x4a }, -+ { CCI_REG8(0x6328), 0x80 }, -+ { CCI_REG8(0x6329), 0x01 }, -+ { CCI_REG8(0x632a), 0x30 }, -+ { CCI_REG8(0x632b), 0x02 }, -+ { CCI_REG8(0x632c), 0x20 }, -+ { CCI_REG8(0x632d), 0x02 }, -+ { CCI_REG8(0x632e), 0x30 }, -+ { CCI_REG8(0x6330), 0x60 }, -+ { CCI_REG8(0x6332), 0x90 }, -+ { CCI_REG8(0x6333), 0x01 }, -+ { CCI_REG8(0x6334), 0x30 }, -+ { CCI_REG8(0x6335), 0x02 }, -+ { CCI_REG8(0x6336), 0x20 }, -+ { CCI_REG8(0x6338), 0x80 }, -+ { CCI_REG8(0x633a), 0xa0 }, -+ { CCI_REG8(0x633b), 0x01 }, -+ { CCI_REG8(0x633c), 0x60 }, -+ { CCI_REG8(0x633d), 0x02 }, -+ { CCI_REG8(0x633e), 0x60 }, -+ { CCI_REG8(0x633f), 0x01 }, -+ { CCI_REG8(0x6340), 0x30 }, -+ { CCI_REG8(0x6341), 0x02 }, -+ { CCI_REG8(0x6342), 0x20 }, -+ { CCI_REG8(0x6343), 0x03 }, -+ { CCI_REG8(0x6344), 0x80 }, -+ { CCI_REG8(0x6345), 0x03 }, -+ { CCI_REG8(0x6346), 0x90 }, -+ { CCI_REG8(0x6348), 0xf0 }, -+ { CCI_REG8(0x6349), 0x01 }, -+ { CCI_REG8(0x634a), 0x20 }, -+ { CCI_REG8(0x634b), 0x02 }, -+ { CCI_REG8(0x634c), 0x10 }, -+ { CCI_REG8(0x634d), 0x03 }, -+ { CCI_REG8(0x634e), 0x60 }, -+ { CCI_REG8(0x6350), 0xa0 }, -+ { CCI_REG8(0x6351), 0x01 }, -+ { CCI_REG8(0x6352), 0x60 }, -+ { CCI_REG8(0x6353), 0x02 }, -+ { CCI_REG8(0x6354), 0x50 }, -+ { CCI_REG8(0x6355), 0x02 }, -+ { CCI_REG8(0x6356), 0x60 }, -+ { CCI_REG8(0x6357), 0x01 }, -+ { CCI_REG8(0x6358), 0x30 }, -+ { CCI_REG8(0x6359), 0x02 }, -+ { CCI_REG8(0x635a), 0x30 }, -+ { CCI_REG8(0x635b), 0x03 }, -+ { CCI_REG8(0x635c), 0x90 }, -+ { CCI_REG8(0x635f), 0x01 }, -+ { CCI_REG8(0x6360), 0x10 }, -+ { CCI_REG8(0x6361), 0x01 }, -+ { CCI_REG8(0x6362), 0x40 }, -+ { CCI_REG8(0x6363), 0x02 }, -+ { CCI_REG8(0x6364), 0x50 }, -+ { CCI_REG8(0x6368), 0x70 }, -+ { CCI_REG8(0x636a), 0xa0 }, -+ { CCI_REG8(0x636b), 0x01 }, -+ { CCI_REG8(0x636c), 0x50 }, -+ { CCI_REG8(0x637d), 0xe4 }, -+ { CCI_REG8(0x637e), 0xb4 }, -+ { CCI_REG8(0x638c), 0x8e }, -+ { CCI_REG8(0x638d), 0x38 }, -+ { CCI_REG8(0x638e), 0xe3 }, -+ { CCI_REG8(0x638f), 0x4c }, -+ { CCI_REG8(0x6390), 0x30 }, -+ { CCI_REG8(0x6391), 0xc3 }, -+ { CCI_REG8(0x6392), 0xae }, -+ { CCI_REG8(0x6393), 0xba }, -+ { CCI_REG8(0x6394), 0xeb }, -+ { CCI_REG8(0x6395), 0x6e }, -+ { CCI_REG8(0x6396), 0x34 }, -+ { CCI_REG8(0x6397), 0xe3 }, -+ { CCI_REG8(0x6398), 0xcf }, -+ { CCI_REG8(0x6399), 0x3c }, -+ { CCI_REG8(0x639a), 0xf3 }, -+ { CCI_REG8(0x639b), 0x0c }, -+ { CCI_REG8(0x639c), 0x30 }, -+ { CCI_REG8(0x639d), 0xc1 }, -+ { CCI_REG8(0x63b9), 0xa3 }, -+ { CCI_REG8(0x63ba), 0xfe }, -+ { CCI_REG8(0x7600), 0x01 }, -+ { CCI_REG8(0x79a0), 0x01 }, -+ { CCI_REG8(0x79a1), 0x01 }, -+ { CCI_REG8(0x79a2), 0x01 }, -+ { CCI_REG8(0x79a3), 0x01 }, -+ { CCI_REG8(0x79a4), 0x01 }, -+ { CCI_REG8(0x79a5), 0x20 }, -+ { CCI_REG8(0x79a9), 0x00 }, -+ { CCI_REG8(0x79aa), 0x01 }, -+ { CCI_REG8(0x79ad), 0x00 }, -+ { CCI_REG8(0x79af), 0x00 }, -+ { CCI_REG8(0x8173), 0x01 }, -+ { CCI_REG8(0x835c), 0x01 }, -+ { CCI_REG8(0x8a74), 0x01 }, -+ { CCI_REG8(0x8c1f), 0x00 }, -+ { CCI_REG8(0x8c27), 0x00 }, -+ { CCI_REG8(0x8c3b), 0x03 }, -+ { CCI_REG8(0x9004), 0x0b }, -+ { CCI_REG8(0x920c), 0x6a }, -+ { CCI_REG8(0x920d), 0x22 }, -+ { CCI_REG8(0x920e), 0x6a }, -+ { CCI_REG8(0x920f), 0x23 }, -+ { CCI_REG8(0x9214), 0x6a }, -+ { CCI_REG8(0x9215), 0x20 }, -+ { CCI_REG8(0x9216), 0x6a }, -+ { CCI_REG8(0x9217), 0x21 }, -+ { CCI_REG8(0x9385), 0x3e }, -+ { CCI_REG8(0x9387), 0x1b }, -+ { CCI_REG8(0x938d), 0x4d }, -+ { CCI_REG8(0x938f), 0x43 }, -+ { CCI_REG8(0x9391), 0x1b }, -+ { CCI_REG8(0x9395), 0x4d }, -+ { CCI_REG8(0x9397), 0x43 }, -+ { CCI_REG8(0x9399), 0x1b }, -+ { CCI_REG8(0x939d), 0x3e }, -+ { CCI_REG8(0x939f), 0x2f }, -+ { CCI_REG8(0x93a5), 0x43 }, -+ { CCI_REG8(0x93a7), 0x2f }, -+ { CCI_REG8(0x93a9), 0x2f }, -+ { CCI_REG8(0x93ad), 0x34 }, -+ { CCI_REG8(0x93af), 0x2f }, -+ { CCI_REG8(0x93b5), 0x3e }, -+ { CCI_REG8(0x93b7), 0x2f }, -+ { CCI_REG8(0x93bd), 0x4d }, -+ { CCI_REG8(0x93bf), 0x43 }, -+ { CCI_REG8(0x93c1), 0x2f }, -+ { CCI_REG8(0x93c5), 0x4d }, -+ { CCI_REG8(0x93c7), 0x43 }, -+ { CCI_REG8(0x93c9), 0x2f }, -+ { CCI_REG8(0x974b), 0x02 }, -+ { CCI_REG8(0x995c), 0x8c }, -+ { CCI_REG8(0x995d), 0x00 }, -+ { CCI_REG8(0x995e), 0x00 }, -+ { CCI_REG8(0x9963), 0x64 }, -+ { CCI_REG8(0x9964), 0x50 }, -+ { CCI_REG8(0xaa0a), 0x26 }, -+ { CCI_REG8(0xae03), 0x04 }, -+ { CCI_REG8(0xae04), 0x03 }, -+ { CCI_REG8(0xae05), 0x03 }, -+ { CCI_REG8(0xbc1c), 0x08 }, -+ { CCI_REG8(0xbcf1), 0x02 }, -+}; -+ -+/* 16 mpix 10fps */ -+static const struct cci_reg_sequence mode_4656x3496_regs[] = { -+ { CCI_REG8(0x0111), 0x02 }, -+ { CCI_REG8(0x0112), 0x0a }, -+ { CCI_REG8(0x0113), 0x0a }, -+ { CCI_REG8(0x0114), 0x01 }, -+ { CCI_REG8(0x0342), 0x42 }, -+ { CCI_REG8(0x0343), 0x00 }, -+ { CCI_REG8(0x0340), 0x0d }, -+ { CCI_REG8(0x0341), 0xf4 }, -+ { CCI_REG8(0x0344), 0x00 }, -+ { CCI_REG8(0x0345), 0x00 }, -+ { CCI_REG8(0x0346), 0x00 }, -+ { CCI_REG8(0x0347), 0x00 }, -+ { CCI_REG8(0x0348), 0x12 }, -+ { CCI_REG8(0x0349), 0x2f }, -+ { CCI_REG8(0x034a), 0x0d }, -+ { CCI_REG8(0x034b), 0xa7 }, -+ { CCI_REG8(0x0220), 0x00 }, -+ { CCI_REG8(0x0221), 0x11 }, -+ { CCI_REG8(0x0222), 0x01 }, -+ { CCI_REG8(0x0900), 0x00 }, -+ { CCI_REG8(0x0901), 0x11 }, -+ { CCI_REG8(0x0902), 0x0a }, -+ { CCI_REG8(0x3f4c), 0x01 }, -+ { CCI_REG8(0x3f4d), 0x01 }, -+ { CCI_REG8(0x4254), 0x7f }, -+ { CCI_REG8(0x0401), 0x00 }, -+ { CCI_REG8(0x0404), 0x00 }, -+ { CCI_REG8(0x0405), 0x10 }, -+ { CCI_REG8(0x0408), 0x00 }, -+ { CCI_REG8(0x0409), 0x00 }, -+ { CCI_REG8(0x040a), 0x00 }, -+ { CCI_REG8(0x040b), 0x00 }, -+ { CCI_REG8(0x040c), 0x12 }, -+ { CCI_REG8(0x040d), 0x30 }, -+ { CCI_REG8(0x040e), 0x0d }, -+ { CCI_REG8(0x040f), 0xa8 }, -+ { CCI_REG8(0x034c), 0x12 }, -+ { CCI_REG8(0x034d), 0x30 }, -+ { CCI_REG8(0x034e), 0x0d }, -+ { CCI_REG8(0x034f), 0xa8 }, -+ { CCI_REG8(0x0301), 0x06 }, -+ { CCI_REG8(0x0303), 0x04 }, -+ { CCI_REG8(0x0305), 0x04 }, -+ { CCI_REG8(0x0306), 0x01 }, -+ { CCI_REG8(0x0307), 0x57 }, -+ { CCI_REG8(0x0309), 0x0a }, -+ { CCI_REG8(0x030b), 0x02 }, -+ { CCI_REG8(0x030d), 0x04 }, -+ { CCI_REG8(0x030e), 0x01 }, -+ { CCI_REG8(0x030f), 0x49 }, -+ { CCI_REG8(0x0310), 0x01 }, -+ { CCI_REG8(0x0820), 0x07 }, -+ { CCI_REG8(0x0821), 0xb6 }, -+ { CCI_REG8(0x0822), 0x00 }, -+ { CCI_REG8(0x0823), 0x00 }, -+ { CCI_REG8(0x3e20), 0x01 }, -+ { CCI_REG8(0x3e37), 0x00 }, -+ { CCI_REG8(0x3e3b), 0x00 }, -+ { CCI_REG8(0x0106), 0x00 }, -+ { CCI_REG8(0x0b00), 0x00 }, -+ { CCI_REG8(0x3230), 0x00 }, -+ { CCI_REG8(0x3f14), 0x01 }, -+ { CCI_REG8(0x3f3c), 0x01 }, -+ { CCI_REG8(0x3f0d), 0x0a }, -+ { CCI_REG8(0x3fbc), 0x00 }, -+ { CCI_REG8(0x3c06), 0x00 }, -+ { CCI_REG8(0x3c07), 0x48 }, -+ { CCI_REG8(0x3c0a), 0x00 }, -+ { CCI_REG8(0x3c0b), 0x00 }, -+ { CCI_REG8(0x3f78), 0x00 }, -+ { CCI_REG8(0x3f79), 0x40 }, -+ { CCI_REG8(0x3f7c), 0x00 }, -+ { CCI_REG8(0x3f7d), 0x00 }, -+}; -+ -+/* 4k 21fps mode */ -+static const struct cci_reg_sequence mode_3840x2160_regs[] = { -+ { CCI_REG8(0x0111), 0x02 }, -+ { CCI_REG8(0x0112), 0x0a }, -+ { CCI_REG8(0x0113), 0x0a }, -+ { CCI_REG8(0x0114), 0x01 }, -+ { CCI_REG8(0x0342), 0x38 }, -+ { CCI_REG8(0x0343), 0x70 }, -+ { CCI_REG8(0x0340), 0x08 }, -+ { CCI_REG8(0x0341), 0xd4 }, -+ { CCI_REG8(0x0344), 0x01 }, -+ { CCI_REG8(0x0345), 0x98 }, -+ { CCI_REG8(0x0346), 0x02 }, -+ { CCI_REG8(0x0347), 0xa0 }, -+ { CCI_REG8(0x0348), 0x10 }, -+ { CCI_REG8(0x0349), 0x97 }, -+ { CCI_REG8(0x034a), 0x0b }, -+ { CCI_REG8(0x034b), 0x17 }, -+ { CCI_REG8(0x0220), 0x00 }, -+ { CCI_REG8(0x0221), 0x11 }, -+ { CCI_REG8(0x0222), 0x01 }, -+ { CCI_REG8(0x0900), 0x00 }, -+ { CCI_REG8(0x0901), 0x11 }, -+ { CCI_REG8(0x0902), 0x0a }, -+ { CCI_REG8(0x3f4c), 0x01 }, -+ { CCI_REG8(0x3f4d), 0x01 }, -+ { CCI_REG8(0x4254), 0x7f }, -+ { CCI_REG8(0x0401), 0x00 }, -+ { CCI_REG8(0x0404), 0x00 }, -+ { CCI_REG8(0x0405), 0x10 }, -+ { CCI_REG8(0x0408), 0x00 }, -+ { CCI_REG8(0x0409), 0x00 }, -+ { CCI_REG8(0x040a), 0x00 }, -+ { CCI_REG8(0x040b), 0x00 }, -+ { CCI_REG8(0x040c), 0x0f }, -+ { CCI_REG8(0x040d), 0x00 }, -+ { CCI_REG8(0x040e), 0x08 }, -+ { CCI_REG8(0x040f), 0x70 }, -+ { CCI_REG8(0x034c), 0x0f }, -+ { CCI_REG8(0x034d), 0x00 }, -+ { CCI_REG8(0x034e), 0x08 }, -+ { CCI_REG8(0x034f), 0x70 }, -+ { CCI_REG8(0x0301), 0x06 }, -+ { CCI_REG8(0x0303), 0x04 }, -+ { CCI_REG8(0x0305), 0x04 }, -+ { CCI_REG8(0x0306), 0x01 }, -+ { CCI_REG8(0x0307), 0x57 }, -+ { CCI_REG8(0x0309), 0x0a }, -+ { CCI_REG8(0x030b), 0x02 }, -+ { CCI_REG8(0x030d), 0x04 }, -+ { CCI_REG8(0x030e), 0x01 }, -+ { CCI_REG8(0x030f), 0x49 }, -+ { CCI_REG8(0x0310), 0x01 }, -+ { CCI_REG8(0x0820), 0x07 }, -+ { CCI_REG8(0x0821), 0xb6 }, -+ { CCI_REG8(0x0822), 0x00 }, -+ { CCI_REG8(0x0823), 0x00 }, -+ { CCI_REG8(0x3e20), 0x01 }, -+ { CCI_REG8(0x3e37), 0x00 }, -+ { CCI_REG8(0x3e3b), 0x00 }, -+ { CCI_REG8(0x0106), 0x00 }, -+ { CCI_REG8(0x0b00), 0x00 }, -+ { CCI_REG8(0x3230), 0x00 }, -+ { CCI_REG8(0x3f14), 0x01 }, -+ { CCI_REG8(0x3f3c), 0x01 }, -+ { CCI_REG8(0x3f0d), 0x0a }, -+ { CCI_REG8(0x3fbc), 0x00 }, -+ { CCI_REG8(0x3c06), 0x00 }, -+ { CCI_REG8(0x3c07), 0x48 }, -+ { CCI_REG8(0x3c0a), 0x00 }, -+ { CCI_REG8(0x3c0b), 0x00 }, -+ { CCI_REG8(0x3f78), 0x00 }, -+ { CCI_REG8(0x3f79), 0x40 }, -+ { CCI_REG8(0x3f7c), 0x00 }, -+ { CCI_REG8(0x3f7d), 0x00 }, -+}; -+ -+/* 2x2 binned 30fps mode */ -+static const struct cci_reg_sequence mode_2328x1748_regs[] = { -+ { CCI_REG8(0x0111), 0x02 }, -+ { CCI_REG8(0x0112), 0x0a }, -+ { CCI_REG8(0x0113), 0x0a }, -+ { CCI_REG8(0x0114), 0x01 }, -+ { CCI_REG8(0x0342), 0x24 }, -+ { CCI_REG8(0x0343), 0x12 }, -+ { CCI_REG8(0x0340), 0x09 }, -+ { CCI_REG8(0x0341), 0xac }, -+ { CCI_REG8(0x0344), 0x00 }, -+ { CCI_REG8(0x0345), 0x00 }, -+ { CCI_REG8(0x0346), 0x00 }, -+ { CCI_REG8(0x0347), 0x00 }, -+ { CCI_REG8(0x0348), 0x12 }, -+ { CCI_REG8(0x0349), 0x2f }, -+ { CCI_REG8(0x034a), 0x0d }, -+ { CCI_REG8(0x034b), 0xa7 }, -+ { CCI_REG8(0x0220), 0x00 }, -+ { CCI_REG8(0x0221), 0x11 }, -+ { CCI_REG8(0x0222), 0x01 }, -+ { CCI_REG8(0x0900), 0x01 }, -+ { CCI_REG8(0x0901), 0x22 }, -+ { CCI_REG8(0x0902), 0x0a }, -+ { CCI_REG8(0x3f4c), 0x01 }, -+ { CCI_REG8(0x3f4d), 0x01 }, -+ { CCI_REG8(0x4254), 0x7f }, -+ { CCI_REG8(0x0401), 0x00 }, -+ { CCI_REG8(0x0404), 0x00 }, -+ { CCI_REG8(0x0405), 0x10 }, -+ { CCI_REG8(0x0408), 0x00 }, -+ { CCI_REG8(0x0409), 0x00 }, -+ { CCI_REG8(0x040a), 0x00 }, -+ { CCI_REG8(0x040b), 0x00 }, -+ { CCI_REG8(0x040c), 0x09 }, -+ { CCI_REG8(0x040d), 0x18 }, -+ { CCI_REG8(0x040e), 0x06 }, -+ { CCI_REG8(0x040f), 0xd4 }, -+ { CCI_REG8(0x034c), 0x09 }, -+ { CCI_REG8(0x034d), 0x18 }, -+ { CCI_REG8(0x034e), 0x06 }, -+ { CCI_REG8(0x034f), 0xd4 }, -+ { CCI_REG8(0x0301), 0x06 }, -+ { CCI_REG8(0x0303), 0x04 }, -+ { CCI_REG8(0x0305), 0x04 }, -+ { CCI_REG8(0x0306), 0x01 }, -+ { CCI_REG8(0x0307), 0x57 }, -+ { CCI_REG8(0x0309), 0x0a }, -+ { CCI_REG8(0x030b), 0x02 }, -+ { CCI_REG8(0x030d), 0x04 }, -+ { CCI_REG8(0x030e), 0x01 }, -+ { CCI_REG8(0x030f), 0x49 }, -+ { CCI_REG8(0x0310), 0x01 }, -+ { CCI_REG8(0x0820), 0x07 }, -+ { CCI_REG8(0x0821), 0xb6 }, -+ { CCI_REG8(0x0822), 0x00 }, -+ { CCI_REG8(0x0823), 0x00 }, -+ { CCI_REG8(0x3e20), 0x01 }, -+ { CCI_REG8(0x3e37), 0x00 }, -+ { CCI_REG8(0x3e3b), 0x00 }, -+ { CCI_REG8(0x0106), 0x00 }, -+ { CCI_REG8(0x0b00), 0x00 }, -+ { CCI_REG8(0x3230), 0x00 }, -+ { CCI_REG8(0x3f14), 0x01 }, -+ { CCI_REG8(0x3f3c), 0x01 }, -+ { CCI_REG8(0x3f0d), 0x0a }, -+ { CCI_REG8(0x3fbc), 0x00 }, -+ { CCI_REG8(0x3c06), 0x00 }, -+ { CCI_REG8(0x3c07), 0x48 }, -+ { CCI_REG8(0x3c0a), 0x00 }, -+ { CCI_REG8(0x3c0b), 0x00 }, -+ { CCI_REG8(0x3f78), 0x00 }, -+ { CCI_REG8(0x3f79), 0x40 }, -+ { CCI_REG8(0x3f7c), 0x00 }, -+ { CCI_REG8(0x3f7d), 0x00 }, -+}; -+ -+/* 1080p 60fps mode */ -+static const struct cci_reg_sequence mode_1920x1080_regs[] = { -+ { CCI_REG8(0x0111), 0x02 }, -+ { CCI_REG8(0x0112), 0x0a }, -+ { CCI_REG8(0x0113), 0x0a }, -+ { CCI_REG8(0x0114), 0x01 }, -+ { CCI_REG8(0x0342), 0x25 }, -+ { CCI_REG8(0x0343), 0xd9 }, -+ { CCI_REG8(0x0340), 0x04 }, -+ { CCI_REG8(0x0341), 0x9c }, -+ { CCI_REG8(0x0344), 0x01 }, -+ { CCI_REG8(0x0345), 0x98 }, -+ { CCI_REG8(0x0346), 0x02 }, -+ { CCI_REG8(0x0347), 0xa2 }, -+ { CCI_REG8(0x0348), 0x10 }, -+ { CCI_REG8(0x0349), 0x97 }, -+ { CCI_REG8(0x034a), 0x0b }, -+ { CCI_REG8(0x034b), 0x15 }, -+ { CCI_REG8(0x0220), 0x00 }, -+ { CCI_REG8(0x0221), 0x11 }, -+ { CCI_REG8(0x0222), 0x01 }, -+ { CCI_REG8(0x0900), 0x01 }, -+ { CCI_REG8(0x0901), 0x22 }, -+ { CCI_REG8(0x0902), 0x0a }, -+ { CCI_REG8(0x3f4c), 0x01 }, -+ { CCI_REG8(0x3f4d), 0x01 }, -+ { CCI_REG8(0x4254), 0x7f }, -+ { CCI_REG8(0x0401), 0x00 }, -+ { CCI_REG8(0x0404), 0x00 }, -+ { CCI_REG8(0x0405), 0x10 }, -+ { CCI_REG8(0x0408), 0x00 }, -+ { CCI_REG8(0x0409), 0x00 }, -+ { CCI_REG8(0x040a), 0x00 }, -+ { CCI_REG8(0x040b), 0x00 }, -+ { CCI_REG8(0x040c), 0x07 }, -+ { CCI_REG8(0x040d), 0x80 }, -+ { CCI_REG8(0x040e), 0x04 }, -+ { CCI_REG8(0x040f), 0x38 }, -+ { CCI_REG8(0x034c), 0x07 }, -+ { CCI_REG8(0x034d), 0x80 }, -+ { CCI_REG8(0x034e), 0x04 }, -+ { CCI_REG8(0x034f), 0x38 }, -+ { CCI_REG8(0x0301), 0x06 }, -+ { CCI_REG8(0x0303), 0x04 }, -+ { CCI_REG8(0x0305), 0x04 }, -+ { CCI_REG8(0x0306), 0x01 }, -+ { CCI_REG8(0x0307), 0x57 }, -+ { CCI_REG8(0x0309), 0x0a }, -+ { CCI_REG8(0x030b), 0x02 }, -+ { CCI_REG8(0x030d), 0x04 }, -+ { CCI_REG8(0x030e), 0x01 }, -+ { CCI_REG8(0x030f), 0x49 }, -+ { CCI_REG8(0x0310), 0x01 }, -+ { CCI_REG8(0x0820), 0x07 }, -+ { CCI_REG8(0x0821), 0xb6 }, -+ { CCI_REG8(0x0822), 0x00 }, -+ { CCI_REG8(0x0823), 0x00 }, -+ { CCI_REG8(0x3e20), 0x01 }, -+ { CCI_REG8(0x3e37), 0x00 }, -+ { CCI_REG8(0x3e3b), 0x00 }, -+ { CCI_REG8(0x0106), 0x00 }, -+ { CCI_REG8(0x0b00), 0x00 }, -+ { CCI_REG8(0x3230), 0x00 }, -+ { CCI_REG8(0x3f14), 0x01 }, -+ { CCI_REG8(0x3f3c), 0x01 }, -+ { CCI_REG8(0x3f0d), 0x0a }, -+ { CCI_REG8(0x3fbc), 0x00 }, -+ { CCI_REG8(0x3c06), 0x00 }, -+ { CCI_REG8(0x3c07), 0x48 }, -+ { CCI_REG8(0x3c0a), 0x00 }, -+ { CCI_REG8(0x3c0b), 0x00 }, -+ { CCI_REG8(0x3f78), 0x00 }, -+ { CCI_REG8(0x3f79), 0x40 }, -+ { CCI_REG8(0x3f7c), 0x00 }, -+ { CCI_REG8(0x3f7d), 0x00 }, -+}; -+ -+/* 720p 120fps mode */ -+static const struct cci_reg_sequence mode_1280x720_regs[] = { -+ { CCI_REG8(0x0111), 0x02 }, -+ { CCI_REG8(0x0112), 0x0a }, -+ { CCI_REG8(0x0113), 0x0a }, -+ { CCI_REG8(0x0114), 0x01 }, -+ { CCI_REG8(0x0342), 0x1b }, -+ { CCI_REG8(0x0343), 0x3b }, -+ { CCI_REG8(0x0340), 0x03 }, -+ { CCI_REG8(0x0341), 0x34 }, -+ { CCI_REG8(0x0344), 0x04 }, -+ { CCI_REG8(0x0345), 0x18 }, -+ { CCI_REG8(0x0346), 0x04 }, -+ { CCI_REG8(0x0347), 0x12 }, -+ { CCI_REG8(0x0348), 0x0e }, -+ { CCI_REG8(0x0349), 0x17 }, -+ { CCI_REG8(0x034a), 0x09 }, -+ { CCI_REG8(0x034b), 0xb6 }, -+ { CCI_REG8(0x0220), 0x00 }, -+ { CCI_REG8(0x0221), 0x11 }, -+ { CCI_REG8(0x0222), 0x01 }, -+ { CCI_REG8(0x0900), 0x01 }, -+ { CCI_REG8(0x0901), 0x22 }, -+ { CCI_REG8(0x0902), 0x0a }, -+ { CCI_REG8(0x3f4c), 0x01 }, -+ { CCI_REG8(0x3f4d), 0x01 }, -+ { CCI_REG8(0x4254), 0x7f }, -+ { CCI_REG8(0x0401), 0x00 }, -+ { CCI_REG8(0x0404), 0x00 }, -+ { CCI_REG8(0x0405), 0x10 }, -+ { CCI_REG8(0x0408), 0x00 }, -+ { CCI_REG8(0x0409), 0x00 }, -+ { CCI_REG8(0x040a), 0x00 }, -+ { CCI_REG8(0x040b), 0x00 }, -+ { CCI_REG8(0x040c), 0x05 }, -+ { CCI_REG8(0x040d), 0x00 }, -+ { CCI_REG8(0x040e), 0x02 }, -+ { CCI_REG8(0x040f), 0xd0 }, -+ { CCI_REG8(0x034c), 0x05 }, -+ { CCI_REG8(0x034d), 0x00 }, -+ { CCI_REG8(0x034e), 0x02 }, -+ { CCI_REG8(0x034f), 0xd0 }, -+ { CCI_REG8(0x0301), 0x06 }, -+ { CCI_REG8(0x0303), 0x04 }, -+ { CCI_REG8(0x0305), 0x04 }, -+ { CCI_REG8(0x0306), 0x01 }, -+ { CCI_REG8(0x0307), 0x57 }, -+ { CCI_REG8(0x0309), 0x0a }, -+ { CCI_REG8(0x030b), 0x02 }, -+ { CCI_REG8(0x030d), 0x04 }, -+ { CCI_REG8(0x030e), 0x01 }, -+ { CCI_REG8(0x030f), 0x49 }, -+ { CCI_REG8(0x0310), 0x01 }, -+ { CCI_REG8(0x0820), 0x07 }, -+ { CCI_REG8(0x0821), 0xb6 }, -+ { CCI_REG8(0x0822), 0x00 }, -+ { CCI_REG8(0x0823), 0x00 }, -+ { CCI_REG8(0x3e20), 0x01 }, -+ { CCI_REG8(0x3e37), 0x00 }, -+ { CCI_REG8(0x3e3b), 0x00 }, -+ { CCI_REG8(0x0106), 0x00 }, -+ { CCI_REG8(0x0b00), 0x00 }, -+ { CCI_REG8(0x3230), 0x00 }, -+ { CCI_REG8(0x3f14), 0x01 }, -+ { CCI_REG8(0x3f3c), 0x01 }, -+ { CCI_REG8(0x3f0d), 0x0a }, -+ { CCI_REG8(0x3fbc), 0x00 }, -+ { CCI_REG8(0x3c06), 0x00 }, -+ { CCI_REG8(0x3c07), 0x48 }, -+ { CCI_REG8(0x3c0a), 0x00 }, -+ { CCI_REG8(0x3c0b), 0x00 }, -+ { CCI_REG8(0x3f78), 0x00 }, -+ { CCI_REG8(0x3f79), 0x40 }, -+ { CCI_REG8(0x3f7c), 0x00 }, -+ { CCI_REG8(0x3f7d), 0x00 }, -+}; -+ -+/* Mode configs */ -+static const struct imx519_mode supported_modes_10bit[] = { -+ { -+ .width = 4656, -+ .height = 3496, -+ .line_length_pix = 0x4200, -+ .crop = { -+ .left = IMX519_PIXEL_ARRAY_LEFT, -+ .top = IMX519_PIXEL_ARRAY_TOP, -+ .width = 4656, -+ .height = 3496, -+ }, -+ .timeperframe_min = { -+ .numerator = 100, -+ .denominator = 1000 -+ }, -+ .timeperframe_default = { -+ .numerator = 100, -+ .denominator = 1000 -+ }, -+ .reg_list = { -+ .num_of_regs = ARRAY_SIZE(mode_4656x3496_regs), -+ .regs = mode_4656x3496_regs, -+ } -+ }, -+ { -+ .width = 3840, -+ .height = 2160, -+ .line_length_pix = 0x3870, -+ .crop = { -+ .left = IMX519_PIXEL_ARRAY_LEFT + 408, -+ .top = IMX519_PIXEL_ARRAY_TOP + 672, -+ .width = 3840, -+ .height = 2160, -+ }, -+ .timeperframe_min = { -+ .numerator = 100, -+ .denominator = 2100 -+ }, -+ .timeperframe_default = { -+ .numerator = 100, -+ .denominator = 2100 -+ }, -+ .reg_list = { -+ .num_of_regs = ARRAY_SIZE(mode_3840x2160_regs), -+ .regs = mode_3840x2160_regs, -+ } -+ }, -+ { -+ .width = 2328, -+ .height = 1748, -+ .line_length_pix = 0x2412, -+ .crop = { -+ .left = IMX519_PIXEL_ARRAY_LEFT, -+ .top = IMX519_PIXEL_ARRAY_TOP, -+ .width = 4656, -+ .height = 3496, -+ }, -+ .timeperframe_min = { -+ .numerator = 100, -+ .denominator = 3000 -+ }, -+ .timeperframe_default = { -+ .numerator = 100, -+ .denominator = 3000 -+ }, -+ .reg_list = { -+ .num_of_regs = ARRAY_SIZE(mode_2328x1748_regs), -+ .regs = mode_2328x1748_regs, -+ } -+ }, -+ { -+ .width = 1920, -+ .height = 1080, -+ .line_length_pix = 0x25D9, -+ .crop = { -+ .left = IMX519_PIXEL_ARRAY_LEFT + 408, -+ .top = IMX519_PIXEL_ARRAY_TOP + 674, -+ .width = 3840, -+ .height = 2160, -+ }, -+ .timeperframe_min = { -+ .numerator = 100, -+ .denominator = 6000 -+ }, -+ .timeperframe_default = { -+ .numerator = 100, -+ .denominator = 6000 -+ }, -+ .reg_list = { -+ .num_of_regs = ARRAY_SIZE(mode_1920x1080_regs), -+ .regs = mode_1920x1080_regs, -+ } -+ }, -+ { -+ .width = 1280, -+ .height = 720, -+ .line_length_pix = 0x1B3B, -+ .crop = { -+ .left = IMX519_PIXEL_ARRAY_LEFT + 1048, -+ .top = IMX519_PIXEL_ARRAY_TOP + 1042, -+ .width = 2560, -+ .height = 1440, -+ }, -+ .timeperframe_min = { -+ .numerator = 100, -+ .denominator = 12000 -+ }, -+ .timeperframe_default = { -+ .numerator = 100, -+ .denominator = 12000 -+ }, -+ .reg_list = { -+ .num_of_regs = ARRAY_SIZE(mode_1280x720_regs), -+ .regs = mode_1280x720_regs, -+ } -+ } -+}; -+ -+/* -+ * The supported formats. -+ * This table MUST contain 4 entries per format, to cover the various flip -+ * combinations in the order -+ * - no flip -+ * - h flip -+ * - v flip -+ * - h&v flips -+ */ -+static const u32 imx519_mbus_formats[] = { -+ /* 10-bit modes. */ -+ MEDIA_BUS_FMT_SRGGB10_1X10, -+ MEDIA_BUS_FMT_SGRBG10_1X10, -+ MEDIA_BUS_FMT_SGBRG10_1X10, -+ MEDIA_BUS_FMT_SBGGR10_1X10, -+}; -+ -+static const char * const imx519_test_pattern_menu[] = { -+ "Disabled", -+ "Color Bars", -+ "Solid Color", -+ "Grey Color Bars", -+ "PN9" -+}; -+ -+static const int imx519_test_pattern_val[] = { -+ IMX519_TEST_PATTERN_DISABLE, -+ IMX519_TEST_PATTERN_COLOR_BARS, -+ IMX519_TEST_PATTERN_SOLID_COLOR, -+ IMX519_TEST_PATTERN_GREY_COLOR, -+ IMX519_TEST_PATTERN_PN9, -+}; -+ -+/* regulator supplies */ -+static const char * const imx519_supply_name[] = { -+ /* Supplies can be enabled in any order */ -+ "vana", /* Analog (2.8V) supply */ -+ "vdig", /* Digital Core (1.05V) supply */ -+ "vddl", /* IF (1.8V) supply */ -+}; -+ -+/* -+ * Initialisation delay between XCLR low->high and the moment when the sensor -+ * can start capture (i.e. can leave software standby), given by T7 in the -+ * datasheet is 8ms. This does include I2C setup time as well. -+ * -+ * Note, that delay between XCLR low->high and reading the CCI ID register (T6 -+ * in the datasheet) is much smaller - 600us. -+ */ -+#define IMX519_XCLR_MIN_DELAY_US 8000 -+#define IMX519_XCLR_DELAY_RANGE_US 1000 -+ -+struct imx519 { -+ struct v4l2_subdev sd; -+ struct media_pad pad; -+ -+ struct regmap *regmap; -+ struct clk *xclk; -+ -+ struct gpio_desc *reset_gpio; -+ struct regulator_bulk_data supplies[ARRAY_SIZE(imx519_supply_name)]; -+ -+ struct v4l2_ctrl_handler ctrl_handler; -+ /* V4L2 Controls */ -+ struct v4l2_ctrl *link_freq; -+ struct v4l2_ctrl *exposure; -+ struct v4l2_ctrl *vflip; -+ struct v4l2_ctrl *hflip; -+ struct v4l2_ctrl *vblank; -+ struct v4l2_ctrl *hblank; -+ -+ /* Current mode */ -+ const struct imx519_mode *mode; -+ -+ /* Rewrite common registers on stream on? */ -+ bool common_regs_written; -+ -+ /* Current long exposure factor in use. Set through V4L2_CID_VBLANK */ -+ unsigned int long_exp_shift; -+}; -+ -+static inline struct imx519 *to_imx519(struct v4l2_subdev *sd) -+{ -+ return container_of(sd, struct imx519, sd); -+} -+ -+/* Get bayer order based on flip setting. */ -+static u32 imx519_get_format_code(struct imx519 *imx519) -+{ -+ unsigned int i; -+ -+ i = (imx519->vflip->val ? 2 : 0) | -+ (imx519->hflip->val ? 1 : 0); -+ -+ return imx519_mbus_formats[i]; -+} -+ -+static void imx519_adjust_exposure_range(struct imx519 *imx519) -+{ -+ int exposure_max, exposure_def; -+ -+ /* Honour the VBLANK limits when setting exposure. */ -+ exposure_max = imx519->mode->height + imx519->vblank->val - -+ IMX519_EXPOSURE_OFFSET; -+ exposure_def = min(exposure_max, imx519->exposure->val); -+ __v4l2_ctrl_modify_range(imx519->exposure, imx519->exposure->minimum, -+ exposure_max, imx519->exposure->step, -+ exposure_def); -+} -+ -+static int imx519_set_frame_length(struct imx519 *imx519, unsigned int val) -+{ -+ int ret = 0; -+ -+ imx519->long_exp_shift = 0; -+ -+ while (val > IMX519_FRAME_LENGTH_MAX) { -+ imx519->long_exp_shift++; -+ val >>= 1; -+ } -+ -+ cci_write(imx519->regmap, IMX519_REG_FRAME_LENGTH, val, &ret); -+ if (ret) -+ return ret; -+ -+ cci_write(imx519->regmap, IMX519_LONG_EXP_SHIFT_REG, -+ imx519->long_exp_shift, &ret); -+ -+ return ret; -+} -+ -+static int imx519_set_ctrl(struct v4l2_ctrl *ctrl) -+{ -+ struct imx519 *imx519 = -+ container_of(ctrl->handler, struct imx519, ctrl_handler); -+ struct i2c_client *client = v4l2_get_subdevdata(&imx519->sd); -+ int ret = 0; -+ -+ /* -+ * The VBLANK control may change the limits of usable exposure, so check -+ * and adjust if necessary. -+ */ -+ if (ctrl->id == V4L2_CID_VBLANK) -+ imx519_adjust_exposure_range(imx519); -+ -+ /* -+ * Applying V4L2 control value only happens -+ * when power is up for streaming -+ */ -+ if (pm_runtime_get_if_in_use(&client->dev) == 0) -+ return 0; -+ -+ switch (ctrl->id) { -+ case V4L2_CID_ANALOGUE_GAIN: -+ cci_write(imx519->regmap, IMX519_REG_ANALOG_GAIN, -+ ctrl->val, &ret); -+ break; -+ case V4L2_CID_EXPOSURE: -+ cci_write(imx519->regmap, IMX519_REG_EXPOSURE, -+ ctrl->val >> imx519->long_exp_shift, &ret); -+ break; -+ case V4L2_CID_DIGITAL_GAIN: -+ cci_write(imx519->regmap, IMX519_REG_DIGITAL_GAIN, -+ ctrl->val, &ret); -+ break; -+ case V4L2_CID_TEST_PATTERN: -+ cci_write(imx519->regmap, IMX519_REG_TEST_PATTERN, -+ imx519_test_pattern_val[ctrl->val], &ret); -+ break; -+ case V4L2_CID_TEST_PATTERN_RED: -+ cci_write(imx519->regmap, IMX519_REG_TEST_PATTERN_R, -+ ctrl->val, &ret); -+ break; -+ case V4L2_CID_TEST_PATTERN_GREENR: -+ cci_write(imx519->regmap, IMX519_REG_TEST_PATTERN_GR, -+ ctrl->val, &ret); -+ break; -+ case V4L2_CID_TEST_PATTERN_BLUE: -+ cci_write(imx519->regmap, IMX519_REG_TEST_PATTERN_B, -+ ctrl->val, &ret); -+ break; -+ case V4L2_CID_TEST_PATTERN_GREENB: -+ cci_write(imx519->regmap, IMX519_REG_TEST_PATTERN_GB, -+ ctrl->val, &ret); -+ break; -+ case V4L2_CID_HFLIP: -+ case V4L2_CID_VFLIP: -+ cci_write(imx519->regmap, IMX519_REG_ORIENTATION, -+ imx519->hflip->val | imx519->vflip->val << 1, &ret); -+ break; -+ case V4L2_CID_VBLANK: -+ ret = imx519_set_frame_length(imx519, -+ imx519->mode->height + ctrl->val); -+ break; -+ default: -+ dev_info(&client->dev, -+ "ctrl(id:0x%x,val:0x%x) is not handled\n", -+ ctrl->id, ctrl->val); -+ ret = -EINVAL; -+ break; -+ } -+ -+ pm_runtime_mark_last_busy(&client->dev); -+ pm_runtime_put_autosuspend(&client->dev); -+ -+ return ret; -+} -+ -+static const struct v4l2_ctrl_ops imx519_ctrl_ops = { -+ .s_ctrl = imx519_set_ctrl, -+}; -+ -+static int imx519_init_cfg(struct v4l2_subdev *sd, -+ struct v4l2_subdev_state *state) -+{ -+ struct imx519 *imx519 = to_imx519(sd); -+ struct v4l2_mbus_framefmt *format; -+ struct v4l2_rect *crop; -+ -+ /* Initialize try_fmt. */ -+ format = v4l2_subdev_get_pad_format(sd, state, 0); -+ format->width = supported_modes_10bit[0].width; -+ format->height = supported_modes_10bit[0].height; -+ format->code = imx519_get_format_code(imx519); -+ format->field = V4L2_FIELD_NONE; -+ format->colorspace = V4L2_COLORSPACE_RAW; -+ format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(format->colorspace); -+ format->quantization = V4L2_QUANTIZATION_FULL_RANGE; -+ format->xfer_func = V4L2_XFER_FUNC_NONE; -+ -+ /* Initialize crop rectangle. */ -+ crop = v4l2_subdev_get_pad_crop(sd, state, 0); -+ crop->top = IMX519_PIXEL_ARRAY_TOP; -+ crop->left = IMX519_PIXEL_ARRAY_LEFT; -+ crop->width = IMX519_PIXEL_ARRAY_WIDTH; -+ crop->height = IMX519_PIXEL_ARRAY_HEIGHT; -+ -+ return 0; -+} -+ -+static int imx519_enum_mbus_code(struct v4l2_subdev *sd, -+ struct v4l2_subdev_state *sd_state, -+ struct v4l2_subdev_mbus_code_enum *code) -+{ -+ struct imx519 *imx519 = to_imx519(sd); -+ -+ if (code->index > 0) -+ return -EINVAL; -+ -+ code->code = imx519_get_format_code(imx519); -+ -+ return 0; -+} -+ -+static int imx519_enum_frame_size(struct v4l2_subdev *sd, -+ struct v4l2_subdev_state *sd_state, -+ struct v4l2_subdev_frame_size_enum *fse) -+{ -+ struct imx519 *imx519 = to_imx519(sd); -+ -+ if (fse->index >= ARRAY_SIZE(supported_modes_10bit)) -+ return -EINVAL; -+ -+ if (fse->code != imx519_get_format_code(imx519)) -+ return -EINVAL; -+ -+ fse->min_width = supported_modes_10bit[fse->index].width; -+ fse->max_width = fse->min_width; -+ fse->min_height = supported_modes_10bit[fse->index].height; -+ fse->max_height = fse->min_height; -+ -+ return 0; -+} -+ -+static void imx519_update_image_pad_format(struct imx519 *imx519, -+ const struct imx519_mode *mode, -+ struct v4l2_subdev_format *fmt) -+{ -+ fmt->format.width = mode->width; -+ fmt->format.height = mode->height; -+ fmt->format.field = V4L2_FIELD_NONE; -+ fmt->format.colorspace = V4L2_COLORSPACE_RAW; -+ fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; -+ fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; -+ fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; -+} -+ -+static -+unsigned int imx519_get_frame_length(const struct imx519_mode *mode, -+ const struct v4l2_fract *timeperframe) -+{ -+ u64 frame_length; -+ -+ frame_length = (u64)timeperframe->numerator * IMX519_PIXEL_RATE; -+ do_div(frame_length, -+ (u64)timeperframe->denominator * mode->line_length_pix); -+ -+ if (WARN_ON(frame_length > IMX519_FRAME_LENGTH_MAX)) -+ frame_length = IMX519_FRAME_LENGTH_MAX; -+ -+ return max_t(unsigned int, frame_length, mode->height); -+} -+ -+static void imx519_set_framing_limits(struct imx519 *imx519) -+{ -+ unsigned int frm_length_min, frm_length_default, hblank; -+ const struct imx519_mode *mode = imx519->mode; -+ -+ frm_length_min = imx519_get_frame_length(mode, &mode->timeperframe_min); -+ frm_length_default = -+ imx519_get_frame_length(mode, &mode->timeperframe_default); -+ -+ /* Default to no long exposure multiplier. */ -+ imx519->long_exp_shift = 0; -+ -+ /* Update limits and set FPS to default */ -+ __v4l2_ctrl_modify_range(imx519->vblank, frm_length_min - mode->height, -+ ((1 << IMX519_LONG_EXP_SHIFT_MAX) * -+ IMX519_FRAME_LENGTH_MAX) - mode->height, -+ 1, frm_length_default - mode->height); -+ -+ /* Setting this will adjust the exposure limits as well. */ -+ __v4l2_ctrl_s_ctrl(imx519->vblank, frm_length_default - mode->height); -+ -+ /* -+ * Currently PPL is fixed to the mode specified value, so hblank -+ * depends on mode->width only, and is not changeable in any -+ * way other than changing the mode. -+ */ -+ hblank = mode->line_length_pix - mode->width; -+ __v4l2_ctrl_modify_range(imx519->hblank, hblank, hblank, 1, hblank); -+} -+ -+static int imx519_set_pad_format(struct v4l2_subdev *sd, -+ struct v4l2_subdev_state *sd_state, -+ struct v4l2_subdev_format *fmt) -+{ -+ struct v4l2_mbus_framefmt *format; -+ const struct imx519_mode *mode; -+ struct imx519 *imx519 = to_imx519(sd); -+ -+ /* Bayer order varies with flips */ -+ fmt->format.code = imx519_get_format_code(imx519); -+ -+ mode = v4l2_find_nearest_size(supported_modes_10bit, -+ ARRAY_SIZE(supported_modes_10bit), -+ width, height, -+ fmt->format.width, -+ fmt->format.height); -+ imx519_update_image_pad_format(imx519, mode, fmt); -+ format = v4l2_subdev_get_pad_format(sd, sd_state, 0); -+ if (imx519->mode == mode && format->code == fmt->format.code) -+ return 0; -+ -+ if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { -+ imx519->mode = mode; -+ imx519_set_framing_limits(imx519); -+ } -+ -+ *format = fmt->format; -+ -+ return 0; -+} -+ -+static int imx519_get_selection(struct v4l2_subdev *sd, -+ struct v4l2_subdev_state *sd_state, -+ struct v4l2_subdev_selection *sel) -+{ -+ switch (sel->target) { -+ case V4L2_SEL_TGT_CROP: { -+ sel->r = *v4l2_subdev_get_pad_crop(sd, sd_state, 0); -+ return 0; -+ } -+ -+ case V4L2_SEL_TGT_NATIVE_SIZE: -+ sel->r.left = 0; -+ sel->r.top = 0; -+ sel->r.width = IMX519_NATIVE_WIDTH; -+ sel->r.height = IMX519_NATIVE_HEIGHT; -+ -+ return 0; -+ -+ case V4L2_SEL_TGT_CROP_DEFAULT: -+ case V4L2_SEL_TGT_CROP_BOUNDS: -+ sel->r.left = IMX519_PIXEL_ARRAY_LEFT; -+ sel->r.top = IMX519_PIXEL_ARRAY_TOP; -+ sel->r.width = IMX519_PIXEL_ARRAY_WIDTH; -+ sel->r.height = IMX519_PIXEL_ARRAY_HEIGHT; -+ -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+ -+/* Start streaming */ -+static int imx519_start_streaming(struct imx519 *imx519, -+ struct v4l2_subdev_state *state) -+{ -+ struct i2c_client *client = v4l2_get_subdevdata(&imx519->sd); -+ const struct imx519_reg_list *reg_list; -+ int ret; -+ -+ ret = pm_runtime_resume_and_get(&client->dev); -+ if (ret < 0) -+ return ret; -+ -+ if (!imx519->common_regs_written) { -+ ret = cci_multi_reg_write(imx519->regmap, mode_common_regs, -+ ARRAY_SIZE(mode_common_regs), NULL); -+ -+ if (ret) { -+ dev_err(&client->dev, "%s failed to set common settings\n", -+ __func__); -+ goto err_rpm_put; -+ } -+ imx519->common_regs_written = true; -+ } -+ -+ /* Apply default values of current mode */ -+ reg_list = &imx519->mode->reg_list; -+ ret = cci_multi_reg_write(imx519->regmap, reg_list->regs, -+ reg_list->num_of_regs, NULL); -+ if (ret) { -+ dev_err(&client->dev, "%s failed to set mode\n", __func__); -+ goto err_rpm_put; -+ } -+ -+ /* Apply customized values from user */ -+ ret = __v4l2_ctrl_handler_setup(imx519->sd.ctrl_handler); -+ if (ret) -+ goto err_rpm_put; -+ -+ /* set stream on register */ -+ ret = cci_write(imx519->regmap, IMX519_REG_MODE_SELECT, -+ IMX519_MODE_STREAMING, NULL); -+ if (ret) -+ goto err_rpm_put; -+ -+ /* vflip and hflip cannot change during streaming */ -+ __v4l2_ctrl_grab(imx519->vflip, true); -+ __v4l2_ctrl_grab(imx519->hflip, true); -+ -+ return 0; -+ -+err_rpm_put: -+ pm_runtime_mark_last_busy(&client->dev); -+ pm_runtime_put_autosuspend(&client->dev); -+ -+ return ret; -+} -+ -+/* Stop streaming */ -+static void imx519_stop_streaming(struct imx519 *imx519) -+{ -+ struct i2c_client *client = v4l2_get_subdevdata(&imx519->sd); -+ int ret; -+ -+ /* set stream off register */ -+ ret = cci_write(imx519->regmap, IMX519_REG_MODE_SELECT, -+ IMX519_MODE_STANDBY, NULL); -+ if (ret) -+ dev_err(&client->dev, "%s failed to set stream\n", __func__); -+ -+ __v4l2_ctrl_grab(imx519->vflip, false); -+ __v4l2_ctrl_grab(imx519->hflip, false); -+ -+ pm_runtime_mark_last_busy(&client->dev); -+ pm_runtime_put_autosuspend(&client->dev); -+} -+ -+static int imx519_set_stream(struct v4l2_subdev *sd, int enable) -+{ -+ struct imx519 *imx519 = to_imx519(sd); -+ struct v4l2_subdev_state *state; -+ int ret = 0; -+ -+ state = v4l2_subdev_lock_and_get_active_state(sd); -+ -+ if (enable) -+ ret = imx519_start_streaming(imx519, state); -+ else -+ imx519_stop_streaming(imx519); -+ -+ v4l2_subdev_unlock_state(state); -+ -+ return ret; -+} -+ -+static const struct v4l2_subdev_core_ops imx519_core_ops = { -+ .subscribe_event = v4l2_ctrl_subdev_subscribe_event, -+ .unsubscribe_event = v4l2_event_subdev_unsubscribe, -+}; -+ -+static const struct v4l2_subdev_video_ops imx519_video_ops = { -+ .s_stream = imx519_set_stream, -+}; -+ -+static const struct v4l2_subdev_pad_ops imx519_pad_ops = { -+ .init_cfg = imx519_init_cfg, -+ .enum_mbus_code = imx519_enum_mbus_code, -+ .get_fmt = v4l2_subdev_get_fmt, -+ .set_fmt = imx519_set_pad_format, -+ .get_selection = imx519_get_selection, -+ .enum_frame_size = imx519_enum_frame_size, -+}; -+ -+static const struct v4l2_subdev_ops imx519_subdev_ops = { -+ .core = &imx519_core_ops, -+ .video = &imx519_video_ops, -+ .pad = &imx519_pad_ops, -+}; -+ -+static const struct media_entity_operations imx519_subdev_entity_ops = { -+ .link_validate = v4l2_subdev_link_validate, -+}; -+ -+/* Power/clock management functions */ -+static int imx519_power_on(struct device *dev) -+{ -+ struct i2c_client *client = to_i2c_client(dev); -+ struct v4l2_subdev *sd = i2c_get_clientdata(client); -+ struct imx519 *imx519 = to_imx519(sd); -+ int ret; -+ -+ ret = regulator_bulk_enable(ARRAY_SIZE(imx519_supply_name), -+ imx519->supplies); -+ if (ret) { -+ dev_err(&client->dev, "%s: failed to enable regulators\n", -+ __func__); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(imx519->xclk); -+ if (ret) { -+ dev_err(&client->dev, "%s: failed to enable clock\n", -+ __func__); -+ goto reg_off; -+ } -+ -+ gpiod_set_value_cansleep(imx519->reset_gpio, 1); -+ usleep_range(IMX519_XCLR_MIN_DELAY_US, -+ IMX519_XCLR_MIN_DELAY_US + IMX519_XCLR_DELAY_RANGE_US); -+ -+ return 0; -+ -+reg_off: -+ regulator_bulk_disable(ARRAY_SIZE(imx519_supply_name), imx519->supplies); -+ -+ return ret; -+} -+ -+static int imx519_power_off(struct device *dev) -+{ -+ struct i2c_client *client = to_i2c_client(dev); -+ struct v4l2_subdev *sd = i2c_get_clientdata(client); -+ struct imx519 *imx519 = to_imx519(sd); -+ -+ gpiod_set_value_cansleep(imx519->reset_gpio, 0); -+ regulator_bulk_disable(ARRAY_SIZE(imx519_supply_name), imx519->supplies); -+ clk_disable_unprepare(imx519->xclk); -+ -+ /* Force reprogramming of the common registers when powered up again. */ -+ imx519->common_regs_written = false; -+ -+ return 0; -+} -+ -+static int imx519_get_regulators(struct imx519 *imx519) -+{ -+ struct i2c_client *client = v4l2_get_subdevdata(&imx519->sd); -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(imx519_supply_name); i++) -+ imx519->supplies[i].supply = imx519_supply_name[i]; -+ -+ return devm_regulator_bulk_get(&client->dev, -+ ARRAY_SIZE(imx519_supply_name), -+ imx519->supplies); -+} -+ -+/* Verify chip ID */ -+static int imx519_identify_module(struct imx519 *imx519) -+{ -+ struct i2c_client *client = v4l2_get_subdevdata(&imx519->sd); -+ int ret; -+ u64 val; -+ -+ ret = cci_read(imx519->regmap, IMX519_REG_CHIP_ID, &val, NULL); -+ if (ret) { -+ dev_err(&client->dev, "failed to read chip id %x, with error %d\n", -+ IMX519_CHIP_ID, ret); -+ return ret; -+ } -+ -+ if (val != IMX519_CHIP_ID) { -+ dev_err(&client->dev, "chip id mismatch: %x!=%llx\n", -+ IMX519_CHIP_ID, val); -+ return -EIO; -+ } -+ -+ dev_info(&client->dev, "Device found is imx%llx\n", val); -+ -+ return 0; -+} -+ -+/* Initialize control handlers */ -+static int imx519_init_controls(struct imx519 *imx519) -+{ -+ struct v4l2_ctrl_handler *ctrl_hdlr; -+ struct i2c_client *client = v4l2_get_subdevdata(&imx519->sd); -+ struct v4l2_fwnode_device_properties props; -+ unsigned int i; -+ int ret; -+ static const u64 link_freq[] = { -+ IMX519_DEFAULT_LINK_FREQ, -+ }; -+ -+ ctrl_hdlr = &imx519->ctrl_handler; -+ ret = v4l2_ctrl_handler_init(ctrl_hdlr, 16); -+ if (ret) -+ return ret; -+ -+ /* By default, PIXEL_RATE is read only */ -+ v4l2_ctrl_new_std(ctrl_hdlr, &imx519_ctrl_ops, V4L2_CID_PIXEL_RATE, -+ IMX519_PIXEL_RATE, IMX519_PIXEL_RATE, 1, -+ IMX519_PIXEL_RATE); -+ -+ imx519->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, NULL, -+ V4L2_CID_LINK_FREQ, -+ ARRAY_SIZE(link_freq) - 1, -+ 0, link_freq); -+ if (imx519->link_freq) -+ imx519->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; -+ -+ /* -+ * Create the controls here, but mode specific limits are setup -+ * in the imx519_set_framing_limits() call below. -+ */ -+ imx519->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx519_ctrl_ops, -+ V4L2_CID_VBLANK, 0, 0xffff, 1, 0); -+ imx519->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx519_ctrl_ops, -+ V4L2_CID_HBLANK, 0, 0xffff, 1, 0); -+ -+ /* HBLANK is read-only for now, but does change with mode. */ -+ if (imx519->hblank) -+ imx519->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; -+ -+ imx519->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx519_ctrl_ops, -+ V4L2_CID_EXPOSURE, -+ IMX519_EXPOSURE_MIN, -+ IMX519_EXPOSURE_MAX, -+ IMX519_EXPOSURE_STEP, -+ IMX519_EXPOSURE_DEFAULT); -+ -+ v4l2_ctrl_new_std(ctrl_hdlr, &imx519_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, -+ IMX519_ANA_GAIN_MIN, IMX519_ANA_GAIN_MAX, -+ IMX519_ANA_GAIN_STEP, IMX519_ANA_GAIN_DEFAULT); -+ -+ v4l2_ctrl_new_std(ctrl_hdlr, &imx519_ctrl_ops, V4L2_CID_DIGITAL_GAIN, -+ IMX519_DGTL_GAIN_MIN, IMX519_DGTL_GAIN_MAX, -+ IMX519_DGTL_GAIN_STEP, IMX519_DGTL_GAIN_DEFAULT); -+ -+ imx519->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx519_ctrl_ops, -+ V4L2_CID_HFLIP, 0, 1, 1, 0); -+ if (imx519->hflip) -+ imx519->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; -+ -+ imx519->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx519_ctrl_ops, -+ V4L2_CID_VFLIP, 0, 1, 1, 0); -+ if (imx519->vflip) -+ imx519->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; -+ -+ v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx519_ctrl_ops, -+ V4L2_CID_TEST_PATTERN, -+ ARRAY_SIZE(imx519_test_pattern_menu) - 1, -+ 0, 0, imx519_test_pattern_menu); -+ for (i = 0; i < 4; i++) { -+ /* -+ * The assumption is that -+ * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1 -+ * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2 -+ * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3 -+ */ -+ v4l2_ctrl_new_std(ctrl_hdlr, &imx519_ctrl_ops, -+ V4L2_CID_TEST_PATTERN_RED + i, -+ IMX519_TEST_PATTERN_COLOUR_MIN, -+ IMX519_TEST_PATTERN_COLOUR_MAX, -+ IMX519_TEST_PATTERN_COLOUR_STEP, -+ IMX519_TEST_PATTERN_COLOUR_MAX); -+ /* The "Solid color" pattern is white by default */ -+ } -+ -+ if (ctrl_hdlr->error) { -+ ret = ctrl_hdlr->error; -+ dev_err(&client->dev, "%s control init failed (%d)\n", -+ __func__, ret); -+ goto error; -+ } -+ -+ ret = v4l2_fwnode_device_parse(&client->dev, &props); -+ if (ret) -+ goto error; -+ -+ ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx519_ctrl_ops, -+ &props); -+ if (ret) -+ goto error; -+ -+ imx519->sd.ctrl_handler = ctrl_hdlr; -+ -+ mutex_lock(imx519->ctrl_handler.lock); -+ -+ /* Setup exposure and frame/line length limits. */ -+ imx519_set_framing_limits(imx519); -+ -+ mutex_unlock(imx519->ctrl_handler.lock); -+ -+ return 0; -+ -+error: -+ v4l2_ctrl_handler_free(ctrl_hdlr); -+ -+ return ret; -+} -+ -+static void imx519_free_controls(struct imx519 *imx519) -+{ -+ v4l2_ctrl_handler_free(imx519->sd.ctrl_handler); -+} -+ -+static int imx519_check_hwcfg(struct device *dev) -+{ -+ struct fwnode_handle *endpoint; -+ struct v4l2_fwnode_endpoint ep_cfg = { -+ .bus_type = V4L2_MBUS_CSI2_DPHY -+ }; -+ int ret = -EINVAL; -+ -+ endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); -+ if (!endpoint) { -+ dev_err(dev, "endpoint node not found\n"); -+ return -EINVAL; -+ } -+ -+ if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg)) { -+ dev_err(dev, "could not parse endpoint\n"); -+ goto out; -+ } -+ -+ /* Check the number of MIPI CSI2 data lanes */ -+ if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2) { -+ dev_err(dev, "only 2 data lanes are currently supported\n"); -+ goto out; -+ } -+ -+ /* Check the link frequency set in device tree */ -+ if (!ep_cfg.nr_of_link_frequencies) { -+ dev_err(dev, "link-frequency property not found in DT\n"); -+ goto out; -+ } -+ -+ if (ep_cfg.nr_of_link_frequencies != 1 || -+ ep_cfg.link_frequencies[0] != IMX519_DEFAULT_LINK_FREQ) { -+ dev_err(dev, "Link frequency not supported: %lld\n", -+ ep_cfg.link_frequencies[0]); -+ goto out; -+ } -+ -+ ret = 0; -+ -+out: -+ v4l2_fwnode_endpoint_free(&ep_cfg); -+ fwnode_handle_put(endpoint); -+ -+ return ret; -+} -+ -+static const struct of_device_id imx519_dt_ids[] = { -+ { .compatible = "sony,imx519" }, -+ { /* sentinel */ } -+}; -+ -+static int imx519_probe(struct i2c_client *client) -+{ -+ struct device *dev = &client->dev; -+ struct imx519 *imx519; -+ u32 xclk_freq; -+ int ret; -+ -+ imx519 = devm_kzalloc(&client->dev, sizeof(*imx519), GFP_KERNEL); -+ if (!imx519) -+ return -ENOMEM; -+ -+ v4l2_i2c_subdev_init(&imx519->sd, client, &imx519_subdev_ops); -+ -+ /* Check the hardware configuration in device tree */ -+ if (imx519_check_hwcfg(dev)) -+ return -EINVAL; -+ -+ imx519->regmap = devm_cci_regmap_init_i2c(client, 16); -+ if (IS_ERR(imx519->regmap)) -+ return dev_err_probe(dev, PTR_ERR(imx519->regmap), -+ "failed to initialize CCI\n"); -+ -+ /* Get system clock (xclk) */ -+ imx519->xclk = devm_clk_get(dev, NULL); -+ if (IS_ERR(imx519->xclk)) -+ return dev_err_probe(dev, PTR_ERR(imx519->xclk), -+ "failed to get xclk\n"); -+ -+ ret = clk_set_rate(imx519->xclk, IMX519_XCLK_FREQ); -+ if (ret < 0) { -+ dev_err(dev, "failed to set xclk rate\n"); -+ return ret; -+ } -+ -+ xclk_freq = clk_get_rate(imx519->xclk); -+ if (xclk_freq != IMX519_XCLK_FREQ) -+ return dev_err_probe(dev, -EINVAL, -+ "xclk frequency not supported: %d Hz\n", -+ xclk_freq); -+ -+ ret = imx519_get_regulators(imx519); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to get regulators\n"); -+ -+ /* Request optional enable pin */ -+ imx519->reset_gpio = devm_gpiod_get_optional(dev, "reset", -+ GPIOD_OUT_HIGH); -+ if (IS_ERR(imx519->reset_gpio)) -+ return dev_err_probe(dev, PTR_ERR(imx519->reset_gpio), -+ "failed to get reset gpio\n"); -+ -+ /* -+ * The sensor must be powered for imx519_identify_module() -+ * to be able to read the CHIP_ID register -+ */ -+ ret = imx519_power_on(dev); -+ if (ret) -+ return ret; -+ -+ ret = imx519_identify_module(imx519); -+ if (ret) -+ goto error_power_off; -+ -+ /* Set default mode to max resolution */ -+ imx519->mode = &supported_modes_10bit[0]; -+ -+ /* -+ * Enable runtime PM. As the device has been powered manually, mark it -+ * as active, and increase the usage count without resuming the device. -+ */ -+ pm_runtime_set_active(dev); -+ pm_runtime_get_noresume(dev); -+ pm_runtime_enable(dev); -+ -+ pm_runtime_set_autosuspend_delay(dev, 1000); -+ pm_runtime_use_autosuspend(dev); -+ -+ /* This needs the pm runtime to be registered. */ -+ ret = imx519_init_controls(imx519); -+ if (ret) -+ goto error_rpm_disable; -+ -+ /* Initialize subdev */ -+ imx519->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | -+ V4L2_SUBDEV_FL_HAS_EVENTS; -+ imx519->sd.entity.ops = &imx519_subdev_entity_ops; -+ imx519->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; -+ -+ /* Initialize source pads */ -+ imx519->pad.flags = MEDIA_PAD_FL_SOURCE; -+ -+ ret = media_entity_pads_init(&imx519->sd.entity, 1, &imx519->pad); -+ if (ret) { -+ dev_err(dev, "failed to init entity pads: %d\n", ret); -+ goto error_handler_free; -+ } -+ -+ imx519->sd.state_lock = imx519->ctrl_handler.lock; -+ ret = v4l2_subdev_init_finalize(&imx519->sd); -+ if (ret < 0) { -+ dev_err(dev, "subdev init error: %d\n", ret); -+ goto error_media_entity; -+ } -+ -+ ret = v4l2_async_register_subdev_sensor(&imx519->sd); -+ if (ret < 0) { -+ dev_err(dev, "failed to register sensor sub-device: %d\n", ret); -+ goto error_subdev_cleanup; -+ } -+ -+ pm_runtime_mark_last_busy(dev); -+ pm_runtime_put_autosuspend(dev); -+ -+ return 0; -+ -+error_subdev_cleanup: -+ v4l2_subdev_cleanup(&imx519->sd); -+ -+error_media_entity: -+ media_entity_cleanup(&imx519->sd.entity); -+ -+error_handler_free: -+ imx519_free_controls(imx519); -+ -+error_rpm_disable: -+ pm_runtime_disable(&client->dev); -+ pm_runtime_put_noidle(&client->dev); -+ -+error_power_off: -+ imx519_power_off(&client->dev); -+ -+ return ret; -+} -+ -+static void imx519_remove(struct i2c_client *client) -+{ -+ struct v4l2_subdev *sd = i2c_get_clientdata(client); -+ struct imx519 *imx519 = to_imx519(sd); -+ -+ v4l2_async_unregister_subdev(sd); -+ v4l2_subdev_cleanup(sd); -+ media_entity_cleanup(&sd->entity); -+ imx519_free_controls(imx519); -+ -+ pm_runtime_disable(&client->dev); -+ if (!pm_runtime_status_suspended(&client->dev)) -+ imx519_power_off(&client->dev); -+ pm_runtime_set_suspended(&client->dev); -+} -+ -+MODULE_DEVICE_TABLE(of, imx519_dt_ids); -+ -+static const struct dev_pm_ops imx519_pm_ops = { -+ SET_RUNTIME_PM_OPS(imx519_power_off, imx519_power_on, NULL) -+}; -+ -+static struct i2c_driver imx519_i2c_driver = { -+ .driver = { -+ .name = "imx519", -+ .of_match_table = imx519_dt_ids, -+ .pm = &imx519_pm_ops, -+ }, -+ .probe = imx519_probe, -+ .remove = imx519_remove, -+}; -+ -+module_i2c_driver(imx519_i2c_driver); -+ -+MODULE_AUTHOR("Lee Jackson "); -+MODULE_DESCRIPTION("Sony IMX519 sensor driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c -index 05ff5fa8095..b11de4797cc 100644 ---- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c -+++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c -@@ -21,7 +21,6 @@ - * interface support. As a result of that it has an - * alternate register layout. - */ --#define IS_LITE (csid->id >= 2 ? 1 : 0) - - #define CSID_HW_VERSION 0x0 - #define HW_VERSION_STEPPING 0 -@@ -35,13 +34,13 @@ - #define CSID_CSI2_RX_IRQ_MASK 0x24 - #define CSID_CSI2_RX_IRQ_CLEAR 0x28 - --#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) ((IS_LITE ? 0x30 : 0x40) \ -+#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) ((csid_is_lite(csid) ? 0x30 : 0x40) \ - + 0x10 * (rdi)) --#define CSID_CSI2_RDIN_IRQ_MASK(rdi) ((IS_LITE ? 0x34 : 0x44) \ -+#define CSID_CSI2_RDIN_IRQ_MASK(rdi) ((csid_is_lite(csid) ? 0x34 : 0x44) \ - + 0x10 * (rdi)) --#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) ((IS_LITE ? 0x38 : 0x48) \ -+#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) ((csid_is_lite(csid) ? 0x38 : 0x48) \ - + 0x10 * (rdi)) --#define CSID_CSI2_RDIN_IRQ_SET(rdi) ((IS_LITE ? 0x3C : 0x4C) \ -+#define CSID_CSI2_RDIN_IRQ_SET(rdi) ((csid_is_lite(csid) ? 0x3C : 0x4C) \ - + 0x10 * (rdi)) - - #define CSID_TOP_IRQ_STATUS 0x70 -@@ -73,7 +72,7 @@ - #define CGC_MODE_DYNAMIC_GATING 0 - #define CGC_MODE_ALWAYS_ON 1 - --#define CSID_RDI_CFG0(rdi) ((IS_LITE ? 0x200 : 0x300) \ -+#define CSID_RDI_CFG0(rdi) ((csid_is_lite(csid) ? 0x200 : 0x300) \ - + 0x100 * (rdi)) - #define RDI_CFG0_BYTE_CNTR_EN 0 - #define RDI_CFG0_FORMAT_MEASURE_EN 1 -@@ -98,32 +97,32 @@ - #define RDI_CFG0_PACKING_FORMAT 30 - #define RDI_CFG0_ENABLE 31 - --#define CSID_RDI_CFG1(rdi) ((IS_LITE ? 0x204 : 0x304)\ -+#define CSID_RDI_CFG1(rdi) ((csid_is_lite(csid) ? 0x204 : 0x304)\ - + 0x100 * (rdi)) - #define RDI_CFG1_TIMESTAMP_STB_SEL 0 - --#define CSID_RDI_CTRL(rdi) ((IS_LITE ? 0x208 : 0x308)\ -+#define CSID_RDI_CTRL(rdi) ((csid_is_lite(csid) ? 0x208 : 0x308)\ - + 0x100 * (rdi)) - #define RDI_CTRL_HALT_CMD 0 - #define HALT_CMD_HALT_AT_FRAME_BOUNDARY 0 - #define HALT_CMD_RESUME_AT_FRAME_BOUNDARY 1 - #define RDI_CTRL_HALT_MODE 2 - --#define CSID_RDI_FRM_DROP_PATTERN(rdi) ((IS_LITE ? 0x20C : 0x30C)\ -+#define CSID_RDI_FRM_DROP_PATTERN(rdi) ((csid_is_lite(csid) ? 0x20C : 0x30C)\ - + 0x100 * (rdi)) --#define CSID_RDI_FRM_DROP_PERIOD(rdi) ((IS_LITE ? 0x210 : 0x310)\ -+#define CSID_RDI_FRM_DROP_PERIOD(rdi) ((csid_is_lite(csid) ? 0x210 : 0x310)\ - + 0x100 * (rdi)) --#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) ((IS_LITE ? 0x214 : 0x314)\ -+#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) ((csid_is_lite(csid) ? 0x214 : 0x314)\ - + 0x100 * (rdi)) --#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) ((IS_LITE ? 0x218 : 0x318)\ -+#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) ((csid_is_lite(csid) ? 0x218 : 0x318)\ - + 0x100 * (rdi)) --#define CSID_RDI_RPP_PIX_DROP_PATTERN(rdi) ((IS_LITE ? 0x224 : 0x324)\ -+#define CSID_RDI_RPP_PIX_DROP_PATTERN(rdi) ((csid_is_lite(csid) ? 0x224 : 0x324)\ - + 0x100 * (rdi)) --#define CSID_RDI_RPP_PIX_DROP_PERIOD(rdi) ((IS_LITE ? 0x228 : 0x328)\ -+#define CSID_RDI_RPP_PIX_DROP_PERIOD(rdi) ((csid_is_lite(csid) ? 0x228 : 0x328)\ - + 0x100 * (rdi)) --#define CSID_RDI_RPP_LINE_DROP_PATTERN(rdi) ((IS_LITE ? 0x22C : 0x32C)\ -+#define CSID_RDI_RPP_LINE_DROP_PATTERN(rdi) ((csid_is_lite(csid) ? 0x22C : 0x32C)\ - + 0x100 * (rdi)) --#define CSID_RDI_RPP_LINE_DROP_PERIOD(rdi) ((IS_LITE ? 0x230 : 0x330)\ -+#define CSID_RDI_RPP_LINE_DROP_PERIOD(rdi) ((csid_is_lite(csid) ? 0x230 : 0x330)\ - + 0x100 * (rdi)) - - #define CSID_TPG_CTRL 0x600 -diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c -index 95873f988f7..d393618ed54 100644 ---- a/drivers/media/platform/qcom/camss/camss-csid.c -+++ b/drivers/media/platform/qcom/camss/camss-csid.c -@@ -897,3 +897,8 @@ void msm_csid_unregister_entity(struct csid_device *csid) - media_entity_cleanup(&csid->subdev.entity); - v4l2_ctrl_handler_free(&csid->ctrls); - } -+ -+inline bool csid_is_lite(struct csid_device *csid) -+{ -+ return csid->camss->res->csid_res[csid->id].is_lite; -+} -diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h -index 30d94eb2eb0..fddccb69da1 100644 ---- a/drivers/media/platform/qcom/camss/camss-csid.h -+++ b/drivers/media/platform/qcom/camss/camss-csid.h -@@ -215,5 +215,12 @@ extern const struct csid_hw_ops csid_ops_4_1; - extern const struct csid_hw_ops csid_ops_4_7; - extern const struct csid_hw_ops csid_ops_gen2; - -+/* -+ * csid_is_lite - Check if CSID is CSID lite. -+ * @csid: CSID Device -+ * -+ * Return whether CSID is CSID lite -+ */ -+bool csid_is_lite(struct csid_device *csid); - - #endif /* QC_MSM_CAMSS_CSID_H */ -diff --git a/drivers/media/platform/qcom/camss/camss-vfe-170.c b/drivers/media/platform/qcom/camss/camss-vfe-170.c -index 0b211fed127..795ac381533 100644 ---- a/drivers/media/platform/qcom/camss/camss-vfe-170.c -+++ b/drivers/media/platform/qcom/camss/camss-vfe-170.c -@@ -627,42 +627,6 @@ static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm) - spin_unlock_irqrestore(&vfe->output_lock, flags); - } - --/* -- * vfe_pm_domain_off - Disable power domains specific to this VFE. -- * @vfe: VFE Device -- */ --static void vfe_pm_domain_off(struct vfe_device *vfe) --{ -- struct camss *camss = vfe->camss; -- -- if (vfe->id >= camss->res->vfe_num) -- return; -- -- device_link_del(camss->genpd_link[vfe->id]); --} -- --/* -- * vfe_pm_domain_on - Enable power domains specific to this VFE. -- * @vfe: VFE Device -- */ --static int vfe_pm_domain_on(struct vfe_device *vfe) --{ -- struct camss *camss = vfe->camss; -- enum vfe_line_id id = vfe->id; -- -- if (id >= camss->res->vfe_num) -- return 0; -- -- camss->genpd_link[id] = device_link_add(camss->dev, camss->genpd[id], -- DL_FLAG_STATELESS | -- DL_FLAG_PM_RUNTIME | -- DL_FLAG_RPM_ACTIVE); -- if (!camss->genpd_link[id]) -- return -EINVAL; -- -- return 0; --} -- - /* - * vfe_queue_buffer - Add empty buffer - * @vid: Video device structure -diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-1.c b/drivers/media/platform/qcom/camss/camss-vfe-4-1.c -index 2911e4126e7..ef6b34c915d 100644 ---- a/drivers/media/platform/qcom/camss/camss-vfe-4-1.c -+++ b/drivers/media/platform/qcom/camss/camss-vfe-4-1.c -@@ -936,7 +936,7 @@ static irqreturn_t vfe_isr(int irq, void *dev) - * vfe_pm_domain_off - Disable power domains specific to this VFE. - * @vfe: VFE Device - */ --static void vfe_pm_domain_off(struct vfe_device *vfe) -+static void vfe_4_1_pm_domain_off(struct vfe_device *vfe) - { - /* nop */ - } -@@ -945,7 +945,7 @@ static void vfe_pm_domain_off(struct vfe_device *vfe) - * vfe_pm_domain_on - Enable power domains specific to this VFE. - * @vfe: VFE Device - */ --static int vfe_pm_domain_on(struct vfe_device *vfe) -+static int vfe_4_1_pm_domain_on(struct vfe_device *vfe) - { - return 0; - } -@@ -999,8 +999,8 @@ const struct vfe_hw_ops vfe_ops_4_1 = { - .hw_version = vfe_hw_version, - .isr_read = vfe_isr_read, - .isr = vfe_isr, -- .pm_domain_off = vfe_pm_domain_off, -- .pm_domain_on = vfe_pm_domain_on, -+ .pm_domain_off = vfe_4_1_pm_domain_off, -+ .pm_domain_on = vfe_4_1_pm_domain_on, - .reg_update_clear = vfe_reg_update_clear, - .reg_update = vfe_reg_update, - .subdev_init = vfe_subdev_init, -diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-7.c b/drivers/media/platform/qcom/camss/camss-vfe-4-7.c -index b65ed0fef59..7655d22a9fd 100644 ---- a/drivers/media/platform/qcom/camss/camss-vfe-4-7.c -+++ b/drivers/media/platform/qcom/camss/camss-vfe-4-7.c -@@ -1103,42 +1103,6 @@ static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) - writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); - } - --/* -- * vfe_pm_domain_off - Disable power domains specific to this VFE. -- * @vfe: VFE Device -- */ --static void vfe_pm_domain_off(struct vfe_device *vfe) --{ -- struct camss *camss; -- -- if (!vfe) -- return; -- -- camss = vfe->camss; -- -- device_link_del(camss->genpd_link[vfe->id]); --} -- --/* -- * vfe_pm_domain_on - Enable power domains specific to this VFE. -- * @vfe: VFE Device -- */ --static int vfe_pm_domain_on(struct vfe_device *vfe) --{ -- struct camss *camss = vfe->camss; -- enum vfe_line_id id = vfe->id; -- -- camss->genpd_link[id] = device_link_add(camss->dev, camss->genpd[id], DL_FLAG_STATELESS | -- DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); -- -- if (!camss->genpd_link[id]) { -- dev_err(vfe->camss->dev, "Failed to add VFE#%d to power domain\n", id); -- return -EINVAL; -- } -- -- return 0; --} -- - static void vfe_violation_read(struct vfe_device *vfe) - { - u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); -diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-8.c b/drivers/media/platform/qcom/camss/camss-vfe-4-8.c -index 7b3805177f0..f52fa30f385 100644 ---- a/drivers/media/platform/qcom/camss/camss-vfe-4-8.c -+++ b/drivers/media/platform/qcom/camss/camss-vfe-4-8.c -@@ -1093,37 +1093,6 @@ static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) - writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); - } - --/* -- * vfe_pm_domain_off - Disable power domains specific to this VFE. -- * @vfe: VFE Device -- */ --static void vfe_pm_domain_off(struct vfe_device *vfe) --{ -- struct camss *camss = vfe->camss; -- -- device_link_del(camss->genpd_link[vfe->id]); --} -- --/* -- * vfe_pm_domain_on - Enable power domains specific to this VFE. -- * @vfe: VFE Device -- */ --static int vfe_pm_domain_on(struct vfe_device *vfe) --{ -- struct camss *camss = vfe->camss; -- enum vfe_line_id id = vfe->id; -- -- camss->genpd_link[id] = device_link_add(camss->dev, camss->genpd[id], DL_FLAG_STATELESS | -- DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); -- -- if (!camss->genpd_link[id]) { -- dev_err(vfe->camss->dev, "Failed to add VFE#%d to power domain\n", id); -- return -EINVAL; -- } -- -- return 0; --} -- - static void vfe_violation_read(struct vfe_device *vfe) - { - u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); -diff --git a/drivers/media/platform/qcom/camss/camss-vfe-480.c b/drivers/media/platform/qcom/camss/camss-vfe-480.c -index f2368b77fc6..dc2735476c8 100644 ---- a/drivers/media/platform/qcom/camss/camss-vfe-480.c -+++ b/drivers/media/platform/qcom/camss/camss-vfe-480.c -@@ -15,31 +15,28 @@ - #include "camss.h" - #include "camss-vfe.h" - --/* VFE 2/3 are lite and have a different register layout */ --#define IS_LITE (vfe->id >= 2 ? 1 : 0) -- - #define VFE_HW_VERSION (0x00) - --#define VFE_GLOBAL_RESET_CMD (IS_LITE ? 0x0c : 0x1c) --#define GLOBAL_RESET_HW_AND_REG (IS_LITE ? BIT(1) : BIT(0)) -+#define VFE_GLOBAL_RESET_CMD (vfe_is_lite(vfe) ? 0x0c : 0x1c) -+#define GLOBAL_RESET_HW_AND_REG (vfe_is_lite(vfe) ? BIT(1) : BIT(0)) - --#define VFE_REG_UPDATE_CMD (IS_LITE ? 0x20 : 0x34) -+#define VFE_REG_UPDATE_CMD (vfe_is_lite(vfe) ? 0x20 : 0x34) - static inline int reg_update_rdi(struct vfe_device *vfe, int n) - { -- return IS_LITE ? BIT(n) : BIT(1 + (n)); -+ return vfe_is_lite(vfe) ? BIT(n) : BIT(1 + (n)); - } - - #define REG_UPDATE_RDI reg_update_rdi --#define VFE_IRQ_CMD (IS_LITE ? 0x24 : 0x38) -+#define VFE_IRQ_CMD (vfe_is_lite(vfe) ? 0x24 : 0x38) - #define IRQ_CMD_GLOBAL_CLEAR BIT(0) - --#define VFE_IRQ_MASK(n) ((IS_LITE ? 0x28 : 0x3c) + (n) * 4) --#define IRQ_MASK_0_RESET_ACK (IS_LITE ? BIT(17) : BIT(0)) --#define IRQ_MASK_0_BUS_TOP_IRQ (IS_LITE ? BIT(4) : BIT(7)) --#define VFE_IRQ_CLEAR(n) ((IS_LITE ? 0x34 : 0x48) + (n) * 4) --#define VFE_IRQ_STATUS(n) ((IS_LITE ? 0x40 : 0x54) + (n) * 4) -+#define VFE_IRQ_MASK(n) ((vfe_is_lite(vfe) ? 0x28 : 0x3c) + (n) * 4) -+#define IRQ_MASK_0_RESET_ACK (vfe_is_lite(vfe) ? BIT(17) : BIT(0)) -+#define IRQ_MASK_0_BUS_TOP_IRQ (vfe_is_lite(vfe) ? BIT(4) : BIT(7)) -+#define VFE_IRQ_CLEAR(n) ((vfe_is_lite(vfe) ? 0x34 : 0x48) + (n) * 4) -+#define VFE_IRQ_STATUS(n) ((vfe_is_lite(vfe) ? 0x40 : 0x54) + (n) * 4) - --#define BUS_REG_BASE (IS_LITE ? 0x1a00 : 0xaa00) -+#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x1a00 : 0xaa00) - - #define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) - #define WM_CGC_OVERRIDE_ALL (0x3FFFFFF) -@@ -49,13 +46,13 @@ static inline int reg_update_rdi(struct vfe_device *vfe, int n) - #define VFE_BUS_IRQ_MASK(n) (BUS_REG_BASE + 0x18 + (n) * 4) - static inline int bus_irq_mask_0_rdi_rup(struct vfe_device *vfe, int n) - { -- return IS_LITE ? BIT(n) : BIT(3 + (n)); -+ return vfe_is_lite(vfe) ? BIT(n) : BIT(3 + (n)); - } - - #define BUS_IRQ_MASK_0_RDI_RUP bus_irq_mask_0_rdi_rup - static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n) - { -- return IS_LITE ? BIT(4 + (n)) : BIT(6 + (n)); -+ return vfe_is_lite(vfe) ? BIT(4 + (n)) : BIT(6 + (n)); - } - - #define BUS_IRQ_MASK_0_COMP_DONE bus_irq_mask_0_comp_done -@@ -90,8 +87,8 @@ static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n) - /* for titan 480, each bus client is hardcoded to a specific path - * and each bus client is part of a hardcoded "comp group" - */ --#define RDI_WM(n) ((IS_LITE ? 0 : 23) + (n)) --#define RDI_COMP_GROUP(n) ((IS_LITE ? 0 : 11) + (n)) -+#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0 : 23) + (n)) -+#define RDI_COMP_GROUP(n) ((vfe_is_lite(vfe) ? 0 : 11) + (n)) - - #define MAX_VFE_OUTPUT_LINES 4 - -@@ -452,42 +449,6 @@ static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm) - spin_unlock_irqrestore(&vfe->output_lock, flags); - } - --/* -- * vfe_pm_domain_off - Disable power domains specific to this VFE. -- * @vfe: VFE Device -- */ --static void vfe_pm_domain_off(struct vfe_device *vfe) --{ -- struct camss *camss = vfe->camss; -- -- if (vfe->id >= camss->res->vfe_num) -- return; -- -- device_link_del(camss->genpd_link[vfe->id]); --} -- --/* -- * vfe_pm_domain_on - Enable power domains specific to this VFE. -- * @vfe: VFE Device -- */ --static int vfe_pm_domain_on(struct vfe_device *vfe) --{ -- struct camss *camss = vfe->camss; -- enum vfe_line_id id = vfe->id; -- -- if (id >= camss->res->vfe_num) -- return 0; -- -- camss->genpd_link[id] = device_link_add(camss->dev, camss->genpd[id], -- DL_FLAG_STATELESS | -- DL_FLAG_PM_RUNTIME | -- DL_FLAG_RPM_ACTIVE); -- if (!camss->genpd_link[id]) -- return -EINVAL; -- -- return 0; --} -- - /* - * vfe_queue_buffer - Add empty buffer - * @vid: Video device structure -diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c -index 4839e2cedfe..b6ec0dc425b 100644 ---- a/drivers/media/platform/qcom/camss/camss-vfe.c -+++ b/drivers/media/platform/qcom/camss/camss-vfe.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -474,6 +475,40 @@ void vfe_isr_reset_ack(struct vfe_device *vfe) - complete(&vfe->reset_complete); - } - -+/* -+ * vfe_pm_domain_off - Disable power domains specific to this VFE. -+ * @vfe: VFE Device -+ */ -+void vfe_pm_domain_off(struct vfe_device *vfe) -+{ -+ if (!vfe->genpd) -+ return; -+ -+ device_link_del(vfe->genpd_link); -+ vfe->genpd_link = NULL; -+} -+ -+/* -+ * vfe_pm_domain_on - Enable power domains specific to this VFE. -+ * @vfe: VFE Device -+ */ -+int vfe_pm_domain_on(struct vfe_device *vfe) -+{ -+ struct camss *camss = vfe->camss; -+ -+ if (!vfe->genpd) -+ return 0; -+ -+ vfe->genpd_link = device_link_add(camss->dev, vfe->genpd, -+ DL_FLAG_STATELESS | -+ DL_FLAG_PM_RUNTIME | -+ DL_FLAG_RPM_ACTIVE); -+ if (!vfe->genpd_link) -+ return -EINVAL; -+ -+ return 0; -+} -+ - static int vfe_match_clock_names(struct vfe_device *vfe, - struct camss_clock *clock) - { -@@ -1347,6 +1382,34 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, - if (!res->line_num) - return -EINVAL; - -+ /* Power domain */ -+ -+ if (res->pd_name) { -+ vfe->genpd = dev_pm_domain_attach_by_name(camss->dev, -+ res->pd_name); -+ if (IS_ERR(vfe->genpd)) { -+ ret = PTR_ERR(vfe->genpd); -+ return ret; -+ } -+ } -+ -+ if (!vfe->genpd && res->has_pd) { -+ /* -+ * Legacy magic index. -+ * Requires -+ * power-domain = , -+ * , -+ * -+ * id must correspondng to the index of the VFE which must -+ * come before the TOP GDSC. VFE Lite has no individually -+ * collapasible domain which is why id < vfe_num is a valid -+ * check. -+ */ -+ vfe->genpd = dev_pm_domain_attach_by_id(camss->dev, id); -+ if (IS_ERR(vfe->genpd)) -+ return PTR_ERR(vfe->genpd); -+ } -+ - vfe->line_num = res->line_num; - vfe->ops->subdev_init(dev, vfe); - -@@ -1469,6 +1532,19 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, - return 0; - } - -+/* -+ * msm_vfe_genpd_cleanup - Cleanup VFE genpd linkages -+ * @vfe: VFE device -+ */ -+void msm_vfe_genpd_cleanup(struct vfe_device *vfe) -+{ -+ if (vfe->genpd_link) -+ device_link_del(vfe->genpd_link); -+ -+ if (vfe->genpd) -+ dev_pm_domain_detach(vfe->genpd, true); -+} -+ - /* - * vfe_link_setup - Setup VFE connections - * @entity: Pointer to media entity structure -@@ -1663,3 +1739,8 @@ void msm_vfe_unregister_entities(struct vfe_device *vfe) - media_entity_cleanup(&sd->entity); - } - } -+ -+bool vfe_is_lite(struct vfe_device *vfe) -+{ -+ return vfe->camss->res->vfe_res[vfe->id].is_lite; -+} -diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h -index 09baded0dcd..0572c9b08e1 100644 ---- a/drivers/media/platform/qcom/camss/camss-vfe.h -+++ b/drivers/media/platform/qcom/camss/camss-vfe.h -@@ -150,6 +150,8 @@ struct vfe_device { - const struct vfe_hw_ops_gen1 *ops_gen1; - struct vfe_isr_ops isr_ops; - struct camss_video_ops video_ops; -+ struct device *genpd; -+ struct device_link *genpd_link; - }; - - struct camss_subdev_resources; -@@ -157,6 +159,8 @@ struct camss_subdev_resources; - int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, - const struct camss_subdev_resources *res, u8 id); - -+void msm_vfe_genpd_cleanup(struct vfe_device *vfe); -+ - int msm_vfe_register_entities(struct vfe_device *vfe, - struct v4l2_device *v4l2_dev); - -@@ -201,6 +205,18 @@ int vfe_reset(struct vfe_device *vfe); - */ - int vfe_disable(struct vfe_line *line); - -+/* -+ * vfe_pm_domain_off - Disable power domains specific to this VFE. -+ * @vfe: VFE Device -+ */ -+void vfe_pm_domain_off(struct vfe_device *vfe); -+ -+/* -+ * vfe_pm_domain_on - Enable power domains specific to this VFE. -+ * @vfe: VFE Device -+ */ -+int vfe_pm_domain_on(struct vfe_device *vfe); -+ - extern const struct vfe_hw_ops vfe_ops_4_1; - extern const struct vfe_hw_ops vfe_ops_4_7; - extern const struct vfe_hw_ops vfe_ops_4_8; -@@ -210,4 +226,14 @@ extern const struct vfe_hw_ops vfe_ops_480; - int vfe_get(struct vfe_device *vfe); - void vfe_put(struct vfe_device *vfe); - -+/* -+ * vfe_is_lite - Return if VFE is VFE lite. -+ * @vfe: VFE Device -+ * -+ * Some VFE lites have a different register layout. -+ * -+ * Return whether VFE is VFE lite -+ */ -+bool vfe_is_lite(struct vfe_device *vfe); -+ - #endif /* QC_MSM_CAMSS_VFE_H */ -diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c -index 8e78dd8d596..3bb23fd2995 100644 ---- a/drivers/media/platform/qcom/camss/camss.c -+++ b/drivers/media/platform/qcom/camss/camss.c -@@ -278,6 +278,7 @@ static const struct camss_subdev_resources vfe_res_8x96[] = { - .reg = { "vfe0" }, - .interrupt = { "vfe0" }, - .line_num = 3, -+ .has_pd = true, - .ops = &vfe_ops_4_7 - }, - -@@ -298,6 +299,7 @@ static const struct camss_subdev_resources vfe_res_8x96[] = { - .reg = { "vfe1" }, - .interrupt = { "vfe1" }, - .line_num = 3, -+ .has_pd = true, - .ops = &vfe_ops_4_7 - } - }; -@@ -468,6 +470,7 @@ static const struct camss_subdev_resources vfe_res_660[] = { - .reg = { "vfe0" }, - .interrupt = { "vfe0" }, - .line_num = 3, -+ .has_pd = true, - .ops = &vfe_ops_4_8 - }, - -@@ -491,6 +494,7 @@ static const struct camss_subdev_resources vfe_res_660[] = { - .reg = { "vfe1" }, - .interrupt = { "vfe1" }, - .line_num = 3, -+ .has_pd = true, - .ops = &vfe_ops_4_8 - } - }; -@@ -634,6 +638,7 @@ static const struct camss_subdev_resources csid_res_845[] = { - { 384000000 } }, - .reg = { "csid2" }, - .interrupt = { "csid2" }, -+ .is_lite = true, - .ops = &csid_ops_gen2 - } - }; -@@ -658,6 +663,7 @@ static const struct camss_subdev_resources vfe_res_845[] = { - .reg = { "vfe0" }, - .interrupt = { "vfe0" }, - .line_num = 4, -+ .has_pd = true, - .ops = &vfe_ops_170 - }, - -@@ -680,6 +686,7 @@ static const struct camss_subdev_resources vfe_res_845[] = { - .reg = { "vfe1" }, - .interrupt = { "vfe1" }, - .line_num = 4, -+ .has_pd = true, - .ops = &vfe_ops_170 - }, - -@@ -700,6 +707,7 @@ static const struct camss_subdev_resources vfe_res_845[] = { - { 384000000 } }, - .reg = { "vfe_lite" }, - .interrupt = { "vfe_lite" }, -+ .is_lite = true, - .line_num = 4, - .ops = &vfe_ops_170 - } -@@ -805,6 +813,7 @@ static const struct camss_subdev_resources csid_res_8250[] = { - { 0 } }, - .reg = { "csid2" }, - .interrupt = { "csid2" }, -+ .is_lite = true, - .ops = &csid_ops_gen2 - }, - /* CSID3 */ -@@ -817,6 +826,7 @@ static const struct camss_subdev_resources csid_res_8250[] = { - { 0 } }, - .reg = { "csid3" }, - .interrupt = { "csid3" }, -+ .is_lite = true, - .ops = &csid_ops_gen2 - } - }; -@@ -839,7 +849,9 @@ static const struct camss_subdev_resources vfe_res_8250[] = { - { 0 } }, - .reg = { "vfe0" }, - .interrupt = { "vfe0" }, -+ .pd_name = "ife0", - .line_num = 3, -+ .has_pd = true, - .ops = &vfe_ops_480 - }, - /* VFE1 */ -@@ -859,7 +871,9 @@ static const struct camss_subdev_resources vfe_res_8250[] = { - { 0 } }, - .reg = { "vfe1" }, - .interrupt = { "vfe1" }, -+ .pd_name = "ife1", - .line_num = 3, -+ .has_pd = true, - .ops = &vfe_ops_480 - }, - /* VFE2 (lite) */ -@@ -878,6 +892,7 @@ static const struct camss_subdev_resources vfe_res_8250[] = { - { 0 } }, - .reg = { "vfe_lite0" }, - .interrupt = { "vfe_lite0" }, -+ .is_lite = true, - .line_num = 4, - .ops = &vfe_ops_480 - }, -@@ -897,6 +912,7 @@ static const struct camss_subdev_resources vfe_res_8250[] = { - { 0 } }, - .reg = { "vfe_lite1" }, - .interrupt = { "vfe_lite1" }, -+ .is_lite = true, - .line_num = 4, - .ops = &vfe_ops_480 - }, -@@ -1196,7 +1212,7 @@ static int camss_init_subdevices(struct camss *camss) - } - - /* note: SM8250 requires VFE to be initialized before CSID */ -- for (i = 0; i < camss->vfe_total_num; i++) { -+ for (i = 0; i < camss->res->vfe_num; i++) { - ret = msm_vfe_subdev_init(camss, &camss->vfe[i], - &res->vfe_res[i], i); - if (ret < 0) { -@@ -1268,7 +1284,7 @@ static int camss_register_entities(struct camss *camss) - goto err_reg_ispif; - } - -- for (i = 0; i < camss->vfe_total_num; i++) { -+ for (i = 0; i < camss->res->vfe_num; i++) { - ret = msm_vfe_register_entities(&camss->vfe[i], - &camss->v4l2_dev); - if (ret < 0) { -@@ -1340,7 +1356,7 @@ static int camss_register_entities(struct camss *camss) - } - } else { - for (i = 0; i < camss->res->csid_num; i++) -- for (k = 0; k < camss->vfe_total_num; k++) -+ for (k = 0; k < camss->res->vfe_num; k++) - for (j = 0; j < camss->vfe[k].line_num; j++) { - struct v4l2_subdev *csid = &camss->csid[i].subdev; - struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; -@@ -1364,7 +1380,7 @@ static int camss_register_entities(struct camss *camss) - return 0; - - err_link: -- i = camss->vfe_total_num; -+ i = camss->res->vfe_num; - err_reg_vfe: - for (i--; i >= 0; i--) - msm_vfe_unregister_entities(&camss->vfe[i]); -@@ -1403,7 +1419,7 @@ static void camss_unregister_entities(struct camss *camss) - - msm_ispif_unregister_entities(camss->ispif); - -- for (i = 0; i < camss->vfe_total_num; i++) -+ for (i = 0; i < camss->res->vfe_num; i++) - msm_vfe_unregister_entities(&camss->vfe[i]); - } - -@@ -1478,7 +1494,9 @@ static const struct media_device_ops camss_media_ops = { - - static int camss_configure_pd(struct camss *camss) - { -+ const struct camss_resources *res = camss->res; - struct device *dev = camss->dev; -+ int vfepd_num; - int i; - int ret; - -@@ -1498,45 +1516,57 @@ static int camss_configure_pd(struct camss *camss) - if (camss->genpd_num == 1) - return 0; - -- camss->genpd = devm_kmalloc_array(dev, camss->genpd_num, -- sizeof(*camss->genpd), GFP_KERNEL); -- if (!camss->genpd) -- return -ENOMEM; -+ /* count the # of VFEs which have flagged power-domain */ -+ for (vfepd_num = i = 0; i < camss->res->vfe_num; i++) { -+ if (res->vfe_res[i].has_pd) -+ vfepd_num++; -+ } - -- camss->genpd_link = devm_kmalloc_array(dev, camss->genpd_num, -- sizeof(*camss->genpd_link), -- GFP_KERNEL); -- if (!camss->genpd_link) -- return -ENOMEM; -+ /* -+ * If the number of power-domains is greater than the number of VFEs -+ * then the additional power-domain is for the entire CAMSS block. -+ */ -+ if (!(camss->genpd_num > vfepd_num)) -+ return 0; - - /* -- * VFE power domains are in the beginning of the list, and while all -- * power domains should be attached, only if TITAN_TOP power domain is -- * found in the list, it should be linked over here. -+ * If a power-domain name is defined try to use it. -+ * It is possible we are running a new kernel with an old dtb so -+ * fallback to indexes even if a pd_name is defined but not found. - */ -- for (i = 0; i < camss->genpd_num; i++) { -- camss->genpd[i] = dev_pm_domain_attach_by_id(camss->dev, i); -- if (IS_ERR(camss->genpd[i])) { -- ret = PTR_ERR(camss->genpd[i]); -+ if (camss->res->pd_name) { -+ camss->genpd = dev_pm_domain_attach_by_name(camss->dev, -+ camss->res->pd_name); -+ if (IS_ERR(camss->genpd)) { -+ ret = PTR_ERR(camss->genpd); - goto fail_pm; - } - } - -- if (i > camss->res->vfe_num) { -- camss->genpd_link[i - 1] = device_link_add(camss->dev, camss->genpd[i - 1], -- DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | -- DL_FLAG_RPM_ACTIVE); -- if (!camss->genpd_link[i - 1]) { -- ret = -EINVAL; -- goto fail_pm; -- } -+ if (!camss->genpd) { -+ /* -+ * Legacy magic index. TITAN_TOP GDSC must be the last -+ * item in the power-domain list. -+ */ -+ camss->genpd = dev_pm_domain_attach_by_id(camss->dev, -+ camss->genpd_num - 1); -+ } -+ if (IS_ERR_OR_NULL(camss->genpd)) { -+ ret = PTR_ERR(camss->genpd); -+ goto fail_pm; -+ } -+ camss->genpd_link = device_link_add(camss->dev, camss->genpd, -+ DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | -+ DL_FLAG_RPM_ACTIVE); -+ if (!camss->genpd_link) { -+ ret = -EINVAL; -+ goto fail_pm; - } - - return 0; - - fail_pm: -- for (--i ; i >= 0; i--) -- dev_pm_domain_detach(camss->genpd[i], true); -+ dev_pm_domain_detach(camss->genpd, true); - - return ret; - } -@@ -1558,18 +1588,25 @@ static int camss_icc_get(struct camss *camss) - return 0; - } - --static void camss_genpd_cleanup(struct camss *camss) -+static void camss_genpd_subdevice_cleanup(struct camss *camss) - { - int i; - -+ for (i = 0; i < camss->res->vfe_num; i++) -+ msm_vfe_genpd_cleanup(&camss->vfe[i]); -+} -+ -+static void camss_genpd_cleanup(struct camss *camss) -+{ - if (camss->genpd_num == 1) - return; - -- if (camss->genpd_num > camss->res->vfe_num) -- device_link_del(camss->genpd_link[camss->genpd_num - 1]); -+ camss_genpd_subdevice_cleanup(camss); -+ -+ if (camss->genpd_link) -+ device_link_del(camss->genpd_link); - -- for (i = 0; i < camss->genpd_num; i++) -- dev_pm_domain_detach(camss->genpd[i], true); -+ dev_pm_domain_detach(camss->genpd, true); - } - - /* -@@ -1612,8 +1649,7 @@ static int camss_probe(struct platform_device *pdev) - return -ENOMEM; - } - -- camss->vfe_total_num = camss->res->vfe_num + camss->res->vfe_lite_num; -- camss->vfe = devm_kcalloc(dev, camss->vfe_total_num, -+ camss->vfe = devm_kcalloc(dev, camss->res->vfe_num, - sizeof(*camss->vfe), GFP_KERNEL); - if (!camss->vfe) - return -ENOMEM; -@@ -1771,12 +1807,12 @@ static const struct camss_resources sdm845_resources = { - .vfe_res = vfe_res_845, - .csiphy_num = ARRAY_SIZE(csiphy_res_845), - .csid_num = ARRAY_SIZE(csid_res_845), -- .vfe_num = 2, -- .vfe_lite_num = 1, -+ .vfe_num = ARRAY_SIZE(vfe_res_845), - }; - - static const struct camss_resources sm8250_resources = { - .version = CAMSS_8250, -+ .pd_name = "top", - .csiphy_res = csiphy_res_8250, - .csid_res = csid_res_8250, - .vfe_res = vfe_res_8250, -@@ -1784,8 +1820,7 @@ static const struct camss_resources sm8250_resources = { - .icc_path_num = ARRAY_SIZE(icc_res_sm8250), - .csiphy_num = ARRAY_SIZE(csiphy_res_8250), - .csid_num = ARRAY_SIZE(csid_res_8250), -- .vfe_num = 2, -- .vfe_lite_num = 2, -+ .vfe_num = ARRAY_SIZE(vfe_res_8250), - }; - - static const struct of_device_id camss_dt_match[] = { -diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h -index 8acad7321c0..a0c2dcc779f 100644 ---- a/drivers/media/platform/qcom/camss/camss.h -+++ b/drivers/media/platform/qcom/camss/camss.h -@@ -48,7 +48,10 @@ struct camss_subdev_resources { - u32 clock_rate[CAMSS_RES_MAX][CAMSS_RES_MAX]; - char *reg[CAMSS_RES_MAX]; - char *interrupt[CAMSS_RES_MAX]; -+ char *pd_name; - u8 line_num; -+ bool has_pd; -+ bool is_lite; - const void *ops; - }; - -@@ -83,6 +86,7 @@ enum icc_count { - - struct camss_resources { - enum camss_version version; -+ const char *pd_name; - const struct camss_subdev_resources *csiphy_res; - const struct camss_subdev_resources *csid_res; - const struct camss_subdev_resources *ispif_res; -@@ -92,7 +96,6 @@ struct camss_resources { - const unsigned int csiphy_num; - const unsigned int csid_num; - const unsigned int vfe_num; -- const unsigned int vfe_lite_num; - }; - - struct camss { -@@ -106,11 +109,10 @@ struct camss { - struct vfe_device *vfe; - atomic_t ref_count; - int genpd_num; -- struct device **genpd; -- struct device_link **genpd_link; -+ struct device *genpd; -+ struct device_link *genpd_link; - struct icc_path *icc_path[ICC_SM8250_COUNT]; - const struct camss_resources *res; -- unsigned int vfe_total_num; - }; - - struct camss_camera_interface { diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c -index 1c6c62a7f7f..2a59d240e14 100644 +index dbd26c3b245..51f469fc85c 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c -@@ -954,7 +954,10 @@ static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) +@@ -953,7 +953,10 @@ static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) ctx->msg_sz = pkt_size; @@ -13635,7 +6974,7 @@ index 1c6c62a7f7f..2a59d240e14 100644 if (err) return err; -@@ -2254,6 +2257,8 @@ static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) +@@ -2257,6 +2260,8 @@ static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) int i, err, domain_id = -1, vmcount; const char *domain; bool secure_dsp; @@ -13644,19 +6983,22 @@ index 1c6c62a7f7f..2a59d240e14 100644 unsigned int vmids[FASTRPC_MAX_VMIDS]; err = of_property_read_string(rdev->of_node, "label", &domain); -@@ -2297,6 +2302,19 @@ static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) +@@ -2299,6 +2304,22 @@ static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) } } + rmem_node = of_parse_phandle(rdev->of_node, "memory-region", 0); + if (domain_id == SDSP_DOMAIN_ID && rmem_node) { ++ u64 src_perms; + rmem = of_reserved_mem_lookup(rmem_node); + if (!rmem) { + err = -EINVAL; + goto fdev_error; + } + -+ qcom_scm_assign_mem(rmem->base, rmem->size, &data->perms, ++ src_perms = BIT(QCOM_SCM_VMID_HLOS) | BIT(QCOM_SCM_VMID_SSC_Q6); ++ ++ qcom_scm_assign_mem(rmem->base, rmem->size, &src_perms, + data->vmperms, data->vmcount); + + } @@ -13665,10 +7007,10 @@ index 1c6c62a7f7f..2a59d240e14 100644 data->secure = secure_dsp; diff --git a/drivers/net/wireless/ath/ath10k/qmi.c b/drivers/net/wireless/ath/ath10k/qmi.c -index 52c1a3de8da..0334be061bc 100644 +index 38e939f572a..21dbc3e1903 100644 --- a/drivers/net/wireless/ath/ath10k/qmi.c +++ b/drivers/net/wireless/ath/ath10k/qmi.c -@@ -807,6 +807,7 @@ ath10k_qmi_ind_register_send_sync_msg(struct ath10k_qmi *qmi) +@@ -808,6 +808,7 @@ ath10k_qmi_ind_register_send_sync_msg(struct ath10k_qmi *qmi) static void ath10k_qmi_event_server_arrive(struct ath10k_qmi *qmi) { struct ath10k *ar = qmi->ar; @@ -13676,7 +7018,7 @@ index 52c1a3de8da..0334be061bc 100644 int ret; ret = ath10k_qmi_ind_register_send_sync_msg(qmi); -@@ -818,9 +819,15 @@ static void ath10k_qmi_event_server_arrive(struct ath10k_qmi *qmi) +@@ -819,9 +820,15 @@ static void ath10k_qmi_event_server_arrive(struct ath10k_qmi *qmi) return; } @@ -13722,7 +7064,7 @@ index d4bce170769..403f35af34c 100644 struct clk_bulk_data; diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig -index f21cb05815e..c37d3f10da1 100644 +index 3e31375491d..a6eb7d1c3d5 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -966,6 +966,14 @@ config BATTERY_UG3105 @@ -13740,7 +7082,7 @@ index f21cb05815e..c37d3f10da1 100644 config CHARGER_QCOM_SMB2 tristate "Qualcomm PMI8998 PMIC charger driver" depends on MFD_SPMI_PMIC -@@ -984,4 +992,18 @@ config FUEL_GAUGE_MM8013 +@@ -985,4 +993,18 @@ config FUEL_GAUGE_MM8013 the state of charge, temperature, cycle count, actual and design capacity, etc. @@ -15574,10 +8916,10 @@ index 00000000000..f070e56dc87 +MODULE_DESCRIPTION("Lenovo Yoga C630 EC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig -index f3ec2469137..6e4b32383ff 100644 +index 550145f8272..ef5af5fc3e4 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig -@@ -1287,6 +1287,14 @@ config REGULATOR_RTQ2208 +@@ -1297,6 +1297,14 @@ config REGULATOR_RTQ2208 and two ldos. It features wide output voltage range from 0.4V to 2.05V and the capability to configure the corresponding power stages. @@ -15593,10 +8935,10 @@ index f3ec2469137..6e4b32383ff 100644 tristate "Samsung S2MPA01 voltage regulator" depends on MFD_SEC_CORE || COMPILE_TEST diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile -index b2b059b5ee5..c573b12a806 100644 +index 46fb569e6be..924350885a9 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile -@@ -150,6 +150,7 @@ obj-$(CONFIG_REGULATOR_RTMV20) += rtmv20-regulator.o +@@ -151,6 +151,7 @@ obj-$(CONFIG_REGULATOR_RTMV20) += rtmv20-regulator.o obj-$(CONFIG_REGULATOR_RTQ2134) += rtq2134-regulator.o obj-$(CONFIG_REGULATOR_RTQ6752) += rtq6752-regulator.o obj-$(CONFIG_REGULATOR_RTQ2208) += rtq2208-regulator.o @@ -16295,6 +9637,18 @@ index 10129095a4c..6d3016e008e 100644 } static const struct of_device_id wled_match_table[] = { +diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h +index 4016fd1d5b4..f3e088b450b 100644 +--- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h ++++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h +@@ -49,6 +49,7 @@ + + /* DISP_CC Reset */ + #define DISP_CC_MDSS_RSCC_BCR 0 ++#define DISP_CC_MDSS_CORE_BCR 1 + + /* DISP_CC GDSCR */ + #define MDSS_GDSC 0 diff --git a/include/dt-bindings/input/qcom,spmi-haptics.h b/include/dt-bindings/input/qcom,spmi-haptics.h new file mode 100644 index 00000000000..14a7e7d1471 @@ -16333,123 +9687,6 @@ index 00000000000..14a7e7d1471 +#define HAP_AUTO_RES_ZXD_EOP 4 + +#endif /* _DT_BINDINGS_QCOM_PMIC_SPMI_HAPTICS_ */ -diff --git a/include/dt-bindings/interconnect/qcom,sm6115.h b/include/dt-bindings/interconnect/qcom,sm6115.h -new file mode 100644 -index 00000000000..a41d3b254c2 ---- /dev/null -+++ b/include/dt-bindings/interconnect/qcom,sm6115.h -@@ -0,0 +1,111 @@ -+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -+/* -+ * Copyright (c) 2020, The Linux Foundation. All rights reserved. -+ * Copyright (c) 2023, Linaro Limited -+ */ -+ -+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H -+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H -+ -+/* BIMC */ -+#define MASTER_AMPSS_M0 0 -+#define MASTER_SNOC_BIMC_RT 1 -+#define MASTER_SNOC_BIMC_NRT 2 -+#define SNOC_BIMC_MAS 3 -+#define MASTER_GRAPHICS_3D 4 -+#define MASTER_TCU_0 5 -+#define SLAVE_EBI_CH0 6 -+#define BIMC_SNOC_SLV 7 -+ -+/* CNOC */ -+#define SNOC_CNOC_MAS 0 -+#define MASTER_QDSS_DAP 1 -+#define SLAVE_AHB2PHY_USB 2 -+#define SLAVE_APSS_THROTTLE_CFG 3 -+#define SLAVE_BIMC_CFG 4 -+#define SLAVE_BOOT_ROM 5 -+#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6 -+#define SLAVE_CAMERA_RT_THROTTLE_CFG 7 -+#define SLAVE_CAMERA_CFG 8 -+#define SLAVE_CLK_CTL 9 -+#define SLAVE_RBCPR_CX_CFG 10 -+#define SLAVE_RBCPR_MX_CFG 11 -+#define SLAVE_CRYPTO_0_CFG 12 -+#define SLAVE_DCC_CFG 13 -+#define SLAVE_DDR_PHY_CFG 14 -+#define SLAVE_DDR_SS_CFG 15 -+#define SLAVE_DISPLAY_CFG 16 -+#define SLAVE_DISPLAY_THROTTLE_CFG 17 -+#define SLAVE_GPU_CFG 18 -+#define SLAVE_GPU_THROTTLE_CFG 19 -+#define SLAVE_HWKM_CORE 20 -+#define SLAVE_IMEM_CFG 21 -+#define SLAVE_IPA_CFG 22 -+#define SLAVE_LPASS 23 -+#define SLAVE_MAPSS 24 -+#define SLAVE_MDSP_MPU_CFG 25 -+#define SLAVE_MESSAGE_RAM 26 -+#define SLAVE_CNOC_MSS 27 -+#define SLAVE_PDM 28 -+#define SLAVE_PIMEM_CFG 29 -+#define SLAVE_PKA_CORE 30 -+#define SLAVE_PMIC_ARB 31 -+#define SLAVE_QDSS_CFG 32 -+#define SLAVE_QM_CFG 33 -+#define SLAVE_QM_MPU_CFG 34 -+#define SLAVE_QPIC 35 -+#define SLAVE_QUP_0 36 -+#define SLAVE_RPM 37 -+#define SLAVE_SDCC_1 38 -+#define SLAVE_SDCC_2 39 -+#define SLAVE_SECURITY 40 -+#define SLAVE_SNOC_CFG 41 -+#define SLAVE_TCSR 42 -+#define SLAVE_TLMM 43 -+#define SLAVE_USB3 44 -+#define SLAVE_VENUS_CFG 45 -+#define SLAVE_VENUS_THROTTLE_CFG 46 -+#define SLAVE_VSENSE_CTRL_CFG 47 -+#define SLAVE_SERVICE_CNOC 48 -+ -+/* SNOC */ -+#define MASTER_CRYPTO_CORE0 0 -+#define MASTER_SNOC_CFG 1 -+#define MASTER_TIC 2 -+#define MASTER_ANOC_SNOC 3 -+#define BIMC_SNOC_MAS 4 -+#define MASTER_PIMEM 5 -+#define MASTER_QDSS_BAM 6 -+#define MASTER_QPIC 7 -+#define MASTER_QUP_0 8 -+#define MASTER_IPA 9 -+#define MASTER_QDSS_ETR 10 -+#define MASTER_SDCC_1 11 -+#define MASTER_SDCC_2 12 -+#define MASTER_USB3 13 -+#define SLAVE_APPSS 14 -+#define SNOC_CNOC_SLV 15 -+#define SLAVE_OCIMEM 16 -+#define SLAVE_PIMEM 17 -+#define SNOC_BIMC_SLV 18 -+#define SLAVE_SERVICE_SNOC 19 -+#define SLAVE_QDSS_STM 20 -+#define SLAVE_TCU 21 -+#define SLAVE_ANOC_SNOC 22 -+ -+/* CLK Virtual */ -+#define MASTER_QUP_CORE_0 0 -+#define SLAVE_QUP_CORE_0 1 -+ -+/* MMRT Virtual */ -+#define MASTER_CAMNOC_HF 0 -+#define MASTER_MDP_PORT0 1 -+#define SLAVE_SNOC_BIMC_RT 2 -+ -+/* MMNRT Virtual */ -+#define MASTER_CAMNOC_SF 0 -+#define MASTER_VIDEO_P0 1 -+#define MASTER_VIDEO_PROC 2 -+#define SLAVE_SNOC_BIMC_NRT 3 -+ -+#endif diff --git a/include/dt-bindings/sound/qcom,q6voice.h b/include/dt-bindings/sound/qcom,q6voice.h new file mode 100644 index 00000000000..825bf7d47fe @@ -16683,7 +9920,7 @@ index 022a520e31f..e8d5ee027b4 100644 + #endif diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig -index 3429419ca69..fe4dd313198 100644 +index 59f9742e9ff..965bdde6bd9 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -252,6 +252,7 @@ config SND_SOC_ALL_CODECS @@ -16702,7 +9939,7 @@ index 3429419ca69..fe4dd313198 100644 help Normally ASoC codec drivers are only built if a machine driver which uses them is also built since they are only usable with a machine -@@ -1882,6 +1884,14 @@ config SND_SOC_TDA7419 +@@ -1886,6 +1888,14 @@ config SND_SOC_TDA7419 depends on I2C select REGMAP_I2C @@ -16717,7 +9954,7 @@ index 3429419ca69..fe4dd313198 100644 config SND_SOC_TFA9879 tristate "NXP Semiconductors TFA9879 amplifier" depends on I2C -@@ -2431,6 +2441,9 @@ config SND_SOC_LPASS_VA_MACRO +@@ -2435,6 +2445,9 @@ config SND_SOC_LPASS_VA_MACRO select REGMAP_MMIO select SND_SOC_LPASS_MACRO_COMMON tristate "Qualcomm VA Macro in LPASS(Low Power Audio SubSystem)" @@ -16728,10 +9965,10 @@ index 3429419ca69..fe4dd313198 100644 config SND_SOC_LPASS_RX_MACRO depends on COMMON_CLK diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile -index 2078bb0d981..3730c959639 100644 +index f53baa2b956..3e1be95d326 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile -@@ -283,6 +283,10 @@ snd-soc-tas2770-objs := tas2770.o +@@ -284,6 +284,10 @@ snd-soc-tas2770-objs := tas2770.o snd-soc-tas2781-comlib-objs := tas2781-comlib.o snd-soc-tas2781-fmwlib-objs := tas2781-fmwlib.o snd-soc-tas2781-i2c-objs := tas2781-i2c.o @@ -16742,7 +9979,7 @@ index 2078bb0d981..3730c959639 100644 snd-soc-tfa9879-objs := tfa9879.o snd-soc-tfa989x-objs := tfa989x.o snd-soc-tlv320adc3xxx-objs := tlv320adc3xxx.o -@@ -387,6 +391,10 @@ snd-soc-tas2780-objs := tas2780.o +@@ -388,6 +392,10 @@ snd-soc-tas2780-objs := tas2780.o # Mux snd-soc-simple-mux-objs := simple-mux.o @@ -16753,7 +9990,7 @@ index 2078bb0d981..3730c959639 100644 obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o -@@ -669,6 +677,7 @@ obj-$(CONFIG_SND_SOC_TAS5805M) += snd-soc-tas5805m.o +@@ -671,6 +679,7 @@ obj-$(CONFIG_SND_SOC_TAS5805M) += snd-soc-tas5805m.o obj-$(CONFIG_SND_SOC_TAS6424) += snd-soc-tas6424.o obj-$(CONFIG_SND_SOC_TDA7419) += snd-soc-tda7419.o obj-$(CONFIG_SND_SOC_TAS2770) += snd-soc-tas2770.o @@ -55653,10 +48890,10 @@ index 5da1934527f..c5b72786178 100644 if (mbhc_cb->compute_impedance) mbhc->impedance_detect = impedance_det_en; diff --git a/sound/soc/codecs/wcd934x.c b/sound/soc/codecs/wcd934x.c -index 1b6e376f383..70a410e61f7 100644 +index 6813268e6a1..aab6fe03858 100644 --- a/sound/soc/codecs/wcd934x.c +++ b/sound/soc/codecs/wcd934x.c -@@ -3014,6 +3014,7 @@ static int wcd934x_mbhc_init(struct snd_soc_component *component) +@@ -3013,6 +3013,7 @@ static int wcd934x_mbhc_init(struct snd_soc_component *component) { struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent); struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); @@ -55664,7 +48901,7 @@ index 1b6e376f383..70a410e61f7 100644 struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids; intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data, -@@ -3037,6 +3038,8 @@ static int wcd934x_mbhc_init(struct snd_soc_component *component) +@@ -3036,6 +3037,8 @@ static int wcd934x_mbhc_init(struct snd_soc_component *component) return -EINVAL; } @@ -55673,7 +48910,7 @@ index 1b6e376f383..70a410e61f7 100644 snd_soc_add_component_controls(component, impedance_detect_controls, ARRAY_SIZE(impedance_detect_controls)); snd_soc_add_component_controls(component, hph_type_detect_controls, -@@ -5891,7 +5894,6 @@ static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd) +@@ -5890,7 +5893,6 @@ static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd) cfg->anc_micbias = MIC_BIAS_2; cfg->v_hs_max = WCD_MBHC_HS_V_MAX; cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS; @@ -55681,8 +48918,25 @@ index 1b6e376f383..70a410e61f7 100644 cfg->linein_th = 5000; cfg->hs_thr = 1700; cfg->hph_thr = 50; +diff --git a/sound/soc/codecs/wsa884x.c b/sound/soc/codecs/wsa884x.c +index f2653df84e4..ac10eb6cfa1 100644 +--- a/sound/soc/codecs/wsa884x.c ++++ b/sound/soc/codecs/wsa884x.c +@@ -1769,6 +1769,12 @@ static int wsa884x_set_stream(struct snd_soc_dai *dai, + void *stream, int direction) + { + struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev); ++ struct sdw_stream_runtime *sruntime = stream; ++ struct sdw_slave *sdw = dev_to_sdw_dev(dai->dev); ++ ++ /* Check if this belongs to same bus */ ++ // if (sdw->bus->dev != sruntime->dev) ++ // return 0; + + wsa884x->sruntime = stream; + diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig -index e7b00d1d9e9..c8356f99d98 100644 +index 762491d6f2f..2845a83f712 100644 --- a/sound/soc/qcom/Kconfig +++ b/sound/soc/qcom/Kconfig @@ -140,6 +140,14 @@ config SND_SOC_QDSP6 @@ -55948,7 +49202,7 @@ index 00000000000..5c204682c76 +#endif /*_Q6_CVS_H */ diff --git a/sound/soc/qcom/qdsp6/q6mvm.c b/sound/soc/qcom/qdsp6/q6mvm.c new file mode 100644 -index 00000000000..9c29abab0fd +index 00000000000..ac8408b3429 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6mvm.c @@ -0,0 +1,162 @@ @@ -56036,7 +49290,7 @@ index 00000000000..9c29abab0fd + + session_name = q6mvm_session_name(path); + if (session_name) -+ strlcpy(cmd.name, session_name, sizeof(cmd.name)); ++ strscpy(cmd.name, session_name, sizeof(cmd.name)); + + mvm = q6voice_session_create(Q6VOICE_SERVICE_MVM, path, &cmd.hdr); + if (IS_ERR(mvm)) @@ -57328,7 +50582,7 @@ index 00000000000..44274bba474 + +#endif /*_Q6_VOICE_H */ diff --git a/sound/soc/qcom/sdm845.c b/sound/soc/qcom/sdm845.c -index 252a0f0819b..09c0b445da6 100644 +index 75701546b6e..d9494ab41a9 100644 --- a/sound/soc/qcom/sdm845.c +++ b/sound/soc/qcom/sdm845.c @@ -366,10 +366,12 @@ static int sdm845_snd_startup(struct snd_pcm_substream *substream) diff --git a/system/hardware/oneplus-enchilada/pkgs.nix b/system/hardware/oneplus-enchilada/pkgs.nix index 8c33119..43d578a 100644 --- a/system/hardware/oneplus-enchilada/pkgs.nix +++ b/system/hardware/oneplus-enchilada/pkgs.nix @@ -124,8 +124,8 @@ in { # ignoreConfigErrors = false; kernelPatches = [ { - name = "linux_6_7"; - patch = ./linux_6_7.patch; + name = "linux_6_8"; + patch = ./linux_6_8.patch; } { name = "config_fixes"; @@ -582,6 +582,9 @@ in { # keys that are unused in this case # (builtin aarch64-linux config is unused too, but i cant disable it) + ACPI_HOTPLUG_CPU.tristate = lib.mkForce null; CEPH_FSCACHE.tristate = lib.mkForce null; + CIFS_FSCACHE.tristate = lib.mkForce null; DRM_NOUVEAU_GSP_DEFAULT.tristate = lib.mkForce null; FSCACHE_STATS.tristate = lib.mkForce null; + SND_AC97_POWER_SAVE_DEFAULT.tristate = lib.mkForce null; SND_HDA_POWER_SAVE_DEFAULT.tristate = lib.mkForce null; ACPI_HOTPLUG_MEMORY.tristate = lib.mkForce null; BCM2835_MBOX.tristate = lib.mkForce null; BCM2835_WDT.tristate = lib.mkForce null; CHROMEOS_TBMC.tristate = lib.mkForce null; CROS_EC.tristate = lib.mkForce null; CROS_EC_I2C.tristate = lib.mkForce null; CROS_EC_SPI.tristate = lib.mkForce null; CROS_KBD_LED_BACKLIGHT.tristate = lib.mkForce null; diff --git a/system/hosts/router/default.nix b/system/hosts/router/default.nix index cdad05f..5c18c5a 100644 --- a/system/hosts/router/default.nix +++ b/system/hosts/router/default.nix @@ -948,6 +948,6 @@ in { { directory = /secrets; mode = "0000"; } # my custom impermanence module doesnt detect it { directory = /var/db/dhcpcd; mode = "0755"; } - { directory = /var/lib/private/kea; mode = "0750"; parentDirectory.mode = "0700"; } + { directory = /var/lib/private/kea; mode = "0750"; defaultPerms.mode = "0700"; } ]; } diff --git a/system/hosts/server/home.nix b/system/hosts/server/home.nix index e758148..9af4473 100644 --- a/system/hosts/server/home.nix +++ b/system/hosts/server/home.nix @@ -114,7 +114,7 @@ in { "https://api.github.com/repos/FAForever/" "https://github.com/nix-community/nix-index-database/releases/download/" # required for server (I suppose since nvfetcher uses fetchTarball here...) - "https://github.com/searxng/searxng/releases/download/" + "https://github.com/searxng/searxng/" # for nginx CF-Connecting-IP config generation "https://www.cloudflare.com/ips-v4" "https://www.cloudflare.com/ips-v6" diff --git a/system/modules/impermanence.nix b/system/modules/impermanence.nix index 6616587..e5816f3 100644 --- a/system/modules/impermanence.nix +++ b/system/modules/impermanence.nix @@ -70,14 +70,14 @@ in { ] ++ lib.optionals config.services.akkoma.enable [ { directory = /var/lib/akkoma; user = "akkoma"; group = "akkoma"; mode = "0700"; } ] ++ lib.optionals config.services.botamusique.enable [ - { directory = /var/lib/private/botamusique; user = "root"; group = "root"; mode = "0750"; parentDirectory.mode = "0700"; } + { directory = /var/lib/private/botamusique; user = "root"; group = "root"; mode = "0750"; defaultPerms.mode = "0700"; } ] ++ lib.optionals config.programs.ccache.enable [ { directory = config.programs.ccache.cacheDir; user = "root"; group = "nixbld"; mode = "0770"; } { directory = /var/cache/sccache; user = "root"; group = "nixbld"; mode = "0770"; } ] ++ lib.optionals config.services.certspotter.enable [ { directory = /var/lib/certspotter; user = "certspotter"; group = "certspotter"; mode = "0755"; } ] ++ lib.optionals (config.services.coop-ofd.enable or false) [ - { directory = /var/lib/private/coop-ofd; mode = "0750"; parentDirectory.mode = "0700"; } + { directory = /var/lib/private/coop-ofd; mode = "0750"; defaultPerms.mode = "0700"; } ] ++ lib.optionals config.services.dovecot2.enable [ { directory = /var/lib/dhparams; user = "root"; group = "root"; mode = "0755"; } { directory = /var/lib/dovecot; user = "root"; group = "root"; mode = "0755"; }